Sandisk Technologies Inc.

Jiyin Xu

Johann Alsmeier

Hiroyuki Kinoshita

Murshed Chowdhury

Jin Liu

Zhenyu Lu

Tadashi Nakamura

Matthias Baenninger

Marika Gunji-Yoneoka

Wenguang Shi

Kazuya Tokunaga

Xiaolong Hu

Koji Miyata

Hiroyuki Ogawa

Christopher John Petti

James K Kai

Gerrit Jan Hemink

Man Lung Mui

George Matamis

Tong Zhang

Henry Chien

Wei Zhao

Daxin Mao

Kazutaka Yoshizawa

Ryoichi Honma

Dai Iwata

Junichi Ariyoshi

Syo Fukata

Yasuaki Yonemochi

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same

A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.

Method of making three-dimensional semiconductor memory device having laterally undulating memory films

An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.

Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

Multi tier three-dimensional memory devices including vertically shared bit lines

A first stack of alternating layers including first insulating layers and first sacrificial material layers is formed on a substrate. Dielectric oxide layers applying compressive stress are formed on the top surface of the first stack and on the bottom surface of the substrate. A second stack of alternating layers including second insulating layers and second sacrificial material layers is formed over the top dielectric oxide layer. After formation of lateral recesses by removal of the first and second sacrificial material layers, a bottom dielectric oxide layer is removed. A conductive material applying a tensile stress is deposited into the backside recesses to form electrically conductive layers. The compressive stress applied by the top dielectric oxide layer partially cancels the tensile stress applied by the electrically conductive layers, and reduces the curvature of the substrate that has a concave bottom surface.

Three-dimensional memory device with stress compensation layer within a word line stack

Growing community of inventors

Yokkaichi, Japan

Jiyin Xu