Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Yonsei University

Jiwoon Park

Jooho Lee

Hyun-Suk Lee

Hojin Lee

Jin-Su Lee

Jungoo Kang

Gihee Cho

Sanghyuck Ahn

Sangyeol Kang

Taekyun Kim

KwangSoo Park

Hongsik Chae

Jaehyurk Choi

Cheheung Kim

Jinhong Kim

Yongsung Kim

Su-Jin Kim

Changsoo Lee

Young-Geun Park

Su-jin Kim

Chulwoo Park

Sunghwa Lee

Jae-Sang Yun

Yong-hee Cho

Woochul Lee

Yeekyeong Jung

Jungho Hwang

Junghee Cho

An electronic device and a manufacturing method including a dielectric layer according to at least some embodiments are disclosed. The electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a first dielectric layer between the first electrode and the second electrode, a second dielectric layer having a rutile phase, a third dielectric layer between the first dielectric layer and the second electrode, and a third dielectric layer between the second dielectric layer and the second electrode and including a material having a higher energy bandgap than a material included in the second dielectric layer.

Electronic device including dielectric layer and method of manufacturing the electronic device

A capacitor includes a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnOdoped with an impurity; a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide; and an upper electrode layer on the dielectric layer.

Capacitor, memory device including the capacitor

Disclosed is a semiconductor device comprising a substrate, a contact structure that penetrates the substrate, a bottom electrode on the substrate and connected to the contact structure, a dielectric layer that covers the bottom electrode, and a top electrode on the bottom electrode. The dielectric layer separates the top electrode from the bottom electrode. The contact structure includes a lower conductive pattern and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern includes a nitride of a first metal implanted with a dopant.

Semiconductor device and method of fabricating the same

Disclosed is an electronic device which includes a plurality of memory devices, a memory controller, a first signal line that makes electrical connection between the memory controller and a first branch point, a second signal line that makes electrical connection between the first branch point and a second branch point, a third signal line that makes electrical connection between the first branch point and a third branch point, a fourth signal line that electrically connects the second branch point and the first memory device, a fifth signal line that electrically connects the second branch point and the second memory device, a sixth signal line that electrically connects the third branch point and the third memory device, and a stub that includes a first end electrically connected with at least one of the plurality of signal lines, and a second end being left open-circuit.

Electric device including branched signal lines, and electric device including printed circuit board

A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

Semiconductor device

A memory system includes a memory controller and M memory chips. The memory controller generates a first data signal having one of 2voltage levels different from each other, where M is a natural number greater than or equal to two, and outputs the first data signal through a first channel. The first data signal represents first data including M bits. The M memory chips are commonly connected to the memory controller through the first channel. When the M memory chips have an enabled state, the M memory chips simultaneously receives the first data signal transmitted through the first channel from the memory controller, and simultaneously obtains the M bits included in the first data based on the first data signal. Each of the M memory chips obtains a respective one of the M bits, and operates based on the respective one of the M bits.

Memory system, method of operating the same and storage device using the same

A storage device is provided. The storage device includes nonvolatile memory devices provided on a printed circuit board (PCB), a connector, a storage controller and at least one first passive filter. The connector is provided in the PCB and includes connection terminals. The storage controller is provided on the PCB, communicates with an external host through the connection terminals and controls the nonvolatile memory devices. The at least one first passive filter is provided in the PCB, is connected between the connector and the storage controller, and performs an equalization on either a signal provided to the storage controller or a signal provided from the storage controller.

Storage devices and methods of operating storage devices

A transmitter includes output drivers respectively corresponding to data transmission lines, driver control logic configured to control the output drivers in response to data pattern information, and a data pattern detector configured to detect a data pattern in relation to at least two data transmission lines among the data transmission lines over a predetermined period of time, and output the data pattern information corresponding to the data pattern.

Transmitter, data communication device including same, and data transmission method

A storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the data signals in parallel to the semiconductor memory device through signal lines. The storage controller includes a first delay circuit that delays the data signals such that some edges of windows of the data signals on the signal lines are desynchronized by first skew offsets which are different from one another.

Semiconductor device and method of manufacturing the same

Provided are an airborne microbial measurement apparatus and a method of measuring the same. The airborne microbial measurement apparatus includes a particle separation device including a main body having a flow space in which airborne microorganism flows and a collection unit separably coupled to one side of the main body to collect the airborne microorganism, a reagent container in which a lysis reagent reacting with the airborne microorganism collected in the collection unit and a luminous material are stored, and a luminescence measurement device for measuring intensity of light emitted after the airborne microorganism reacts with the lysis reagent and the luminous material.

Airborne microbial measurement apparatus and measurement method

A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal. Data storage devices and methods using such nonvolatile memories are also described.

Growing community of inventors

Suwon-si, South Korea

Jiwoon Park