Samsung Electronics Co., Ltd.

Jiwon Yun

Jiwon Kang

Jongmin Baek

Boun Yoon

Sanghoon Ahn

Wookyung You

Sangjine Park

Naein Lee

Byunghee Kim

Byung-Kwon Cho

Hak-Sun Lee

Ki-Hyung Ko

Vietha Nguyen

Songyi Han

YoungWoo Cho

Myunggeun Song

Young-ju Park

Kee Sang Kwon

Inoue Naoya

Junghan Lee

Teawon Kim

Yurim Kim

Yongsuk Tak

A semiconductor apparatus includes a bit line extending in a first horizontal direction on a substrate; a channel layer on the bit line, the channel layer extending in a vertical direction, including a first oxide semiconductor material that includes indium, and having a first side wall and a second side wall; a word line on the first side wall of the channel layer; a contact forming region on a top surface and an upper portion of the second side wall of the channel layer, the contact forming region including a second oxide semiconductor material that includes indium and having a resistivity lower than a resistivity of the channel layer; a contact layer on the contact forming region; and a capacitor structure on a top surface of the contact layer.

Semiconductor apparatus

Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

Planarized interlayer dielectric with air gap isolation

Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

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Hwaseong-si, South Korea

Jiwon Yun