Intel Corporation

Oracle America, Inc.

Jiwei Lu

Koichi Yamada

William Y Chen

Jason M Agron

Chandramouli Banerjee

Abhinav Das

Paul Caprioli

Keqiang Wu

Yong-fong Lee

Abhik Sarkar

Bo A Zhang

Polychronis Xekalakis

Arvind Krishnaswamy

Palanivelrajan Rajan Shanmugavelayutham

Ajay Harikumar

Cheng Zhao

Jose A Baiocchi Paredes

Tugrul Ince

Ashish Bijlani

Palanivelra Shanmugavelayutham

James D Beany

Palaniverlrajan Shanmugavelayutham

Geetha K Vallabhaneni

William Yu-Wei Chen

A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

Memory management method and apparatus

Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.

Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array

Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.

Technologies for scalable translation caching for binary translation systems

Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

Methods and apparatuses relate to emulating architectural performance monitoring in a binary translation system. In one embodiment, a processor includes an architectural performance counter to maintain an architectural value associated with instruction execution, a register to store the architectural value of the architectural performance counter, binary translation logic to embed an architectural value from the architectural performance counter into a stream of translated instructions having a transactional code region and to store the architectural value into the register, and an execution unit to execute the transactional code region of the stream of translated instructions. The binary translation logic is configured to add the architectural value from the register to the architectural performance counter upon completion of the transactional code region of the stream of translated instructions. In one embodiment, a binary translation system overcomes software incompatibilities by using microarchitectural support to transparently and accurately emulate architectural performance counter behavior.

Apparatus and method for architectural performance monitoring in binary translation systems

Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

Techniques for detecting return-oriented programming

Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.

Binary translation for multi-processor and multi-core platforms

An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.

Method and apparatus for page-level monitoring

Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary. Moreover, the product includes program code for fast-forwarding at least one thread so that its state is consistent with the guest instruction boundary.

Support for a non-native application

A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

Binary translation mechanism

Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.

Technologies for shadow stack manipulation for binary translation systems

One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Synchronization in a computing device

A method of reproducing runtime environment for debugging an application is disclosed. The method includes accessing an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of a plurality of events, the plurality of actions, and a time mark of occurrence for each of the plurality of actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file. Further, the method includes running the application and attaching an optimizer, then triggering each of the plurality of actions to occur at each time mark of occurrence associated with the each of the plurality of actions, and analyzing each of the plurality of actions and the plurality of events associated with the each of the plurality of actions, the analyzing includes comparing the events produced by running the application with the plurality of events in the optimizer file. If a fault is produced by the triggering, a debugger is invoked to analyze the fault.

Sampling based runtime optimizer for efficient debugging of applications

A method of reproducing runtime environment for debugging an application includes reading an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of events, actions, and a time mark of occurrence for each of the actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file. Further, the method includes running the application, attaching an optimizer, and triggering each of the actions to occur at a time mark of occurrence associated with each of the actions. Then, each of the actions and associated events is analyzed by comparing the events produced by running the application with the events in the optimizer file. If a fault is produced by the triggering, a debugger is invoked to analyze the fault.

Techniques for selectively translating resource requests from a program running on a computer system are disclosed. The resource request may be a request to access a file, library file, API, etc. The resource request may be a system call or library call. The computer program may be non-native to the computer system. Translation of resource requests may occur within the operating system or outside it. A resource request containing a reference to a first path and file name may be selectively translated by altering the resource request to contain a reference to a second path and file name. After selectively translating a request, he request is caused to be serviced. A resource request may be serviced by forwarding it to an operating system, and a result may be sent back to the program.

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Pleasanton, CA, United States of America

Jiwei Lu