Applied Materials, Inc.

Jivko Dinev

Saravjeet Singh

Ajay Kumar

John Patrick Holland

Daniel John Hoffman

Wei-Sheng Lei

Brad Eaton

Paul Brillhart

Alexander Miller Paterson

Richard Charles Fovell

Madhava Rao Yalamanchili

Steven C Shannon

Anisul Haque Khan

Steven Lane

Walter R Merry

Tong Liu

Xiaoping Zhou

Roy C Nangoy

Aparna Iyer

Rohit Mishra

Subhash Deshmukh

Shane C Nevil

Sharma V Pamarthy

Jim Zhongyi He

Puneet Bajaj

Sang In Yi

Khalid Mohiuddin Sirajuddin

Dennis Koosau

Jeffrey William Dietz

Farid Abooameri

Robert Scott Clark

Huutri Dao

Kelly A McDonough

David E Gutierrez

Sonal A Srivastava

Declan Scanlan

Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.

Wafer dicing with etch chamber shield ring for film frame wafer applications

Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).

Increased deposition efficiency and higher chamber conductance with source power increase in an inductively coupled plasma (ICP) chamber

Embodiments of the present invention relate to a plasma chamber having a coil assembly which improves plasma uniformity and improves power coupling to the plasma. One embodiment provides a plasma chamber. The plasma chamber includes a chamber body having sidewalls and a lid, wherein the chamber body defines a processing volume. The plasma chamber further includes a coil assembly disposed over the lid configured to generate inductively coupled plasma within the processing volume, wherein the coil assembly comprises two or more horizontal coils arranged in a common horizontal plane.

High efficiency gas dissociation in inductively coupled plasma reactor with improved uniformity

Apparatus for controlling the temperature of a substrate support may include a first heat transfer loop and a second heat transfer loop. The first heat transfer loop may have a first bath with a first heat transfer fluid at a first temperature. The second heat transfer loop may have a second bath with a second heat transfer fluid at a second temperature. The first and second temperatures may be the same or different. First and second flow controllers may be provided for respectively providing the first and second heat transfer fluids to a substrate support. One or more return lines may couple one or more outlets of the substrate support to the first and second baths for returning the first and second heat transfer fluids to the first and second baths.

Substrate support temperature control

Embodiments of the invention provide a method and apparatus, such as a processing chamber, suitable for etching high aspect ratio features. Other embodiments include a showerhead assembly for use in the processing chamber. In one embodiment, a processing chamber includes a chamber body having a showerhead assembly and substrate support disposed therein. The showerhead assembly includes at least two fluidly isolated plenums, a region transmissive to an optical metrology signal, and a plurality of gas passages formed through the showerhead assembly fluidly coupling the plenums to the interior volume of the chamber body.

Apparatus for etching high aspect ratio features

Embodiments of a method of calculating the equivalent series resistance of a matching network using variable impedance analysis and matching networks analyzed using the same are provided herein. In one embodiment, a method of calculating the equivalent series resistance of a matching network includes the steps of connecting the matching network to a load; measuring an output of the matching network over a range of load impedances; and calculating the equivalent series resistance of the matching network based upon a relationship between the measured output and the load resistance. The load may be a surrogate load or may be a plasma formed in a process chamber.

Matching network characterization using variable impedance analysis

Growing community of inventors

Santa Clara, CA, United States of America

Jivko Dinev