Mstar Semiconductor, Inc.

Jiunn-Yih Lee

Meng-Tse Weng

Po-Nien Lin

Kai Sun

Hsian-Feng Liu

Chun-Wen Yeh

Ke-Chiang Huang

Kuo-Feng Hsu

Jyun-Yang Shih

Wen-Cai Lu

A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

Analog equalizer

A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.

Clock data recovery apparatus and method and phase detector

An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.

Integrated circuit associated with clock generator, and associated control method

A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.

Multi-lane serial link signal receiving system

A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.

Multimedia interface receiving circuit

A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.

Signal receiving apparatus and two-stage adaptive equalization method thereof

A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.

Phase adjustment apparatus and clock generator thereof and method for phase adjustment

The present invention discloses a multi-stage cable equalizer, comprising a fixed gain device and an adjustable gain device. The fixed gain device compensates the loss caused by the cable at a major band, and the adjustable gain device further compensates the loss at adjusted bands. The multi-stage cable equalizer of the present invention exhibits advantages in design flexibility and reduced cost.

Multi-stage cable equalizer

A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes. The device comprises: a programmable equalizer, having a plurality of equalizing modes, receiving an original signal so as to output an equalized signal; a phase-locked loop, receiving a reference clock signal and a first control signal so as to output first sampling pulses and second sampling pulses; a data slicing device, coupled to the phase-locked loop and the programmable equalizer and receiving the first sampling pulses, the second sampling pulses and the equalized signal so as to output a first slicing signal and a second slicing signal; and a signal processing device, coupled to the data slicing device and receiving the first slicing signal and the second slicing signal so as to output the first control signal and a second control signal; wherein the signal processing device programs the programmable equalizer by using the second control signal so as to select an equalizing mode from the plurality of equalizing modes for the programmable equalizer.

Method and device for equalizing mode selection

An apparatus for generating quadrature phase signals in a half-rate data recovery circuit, which is adapted to generate a first and a second clock signals having the same frequency and being 90 degrees out of phase with each other. The apparatus for generating quadrature phase signals mainly comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates, based on a region control signal, a pair of phase region boundaries for the first clock signal as well as a pair of phase region boundaries for the second clock signal by using a plurality of reference clock signals. The first and second phase interpolators perform, based on a position control signal, weighted average processes for the two pairs of phase region boundaries, respectively, to thereby obtain the first and the second clock signals.

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Zhubei, Taiwan

Jiunn-Yih Lee