Mstar Semiconductor, Inc.

Jiunn-Kuang Chen

Sterling Smith

Chieh-Huang Tu

Hung-Yi Lin

Hsu-lin FanChiang

Wen-Ho Hsiao

Chih-Liang Wang

Yun-Hung Shen

Steve Wiyi Yang

Yen-Ting Chen

Yi-Chun Weng

Yuan-Ming Liu

Hsu-Lin FanChiang

An image adjusting method for extending vertical blanking intervals of an image signal is provided. Using the image adjusting method, an adjusted image signal is synchronized with an image signal before the adjustment to prevent image delay. The image adjusting method comprises providing a first image signal having a first data enable signal, wherein the first data enable signal has a first data enable duration; and generating a second data enable signal having a second data enable duration. The first and second data enable durations correspond to a same image frame of an image signal, and the second data enable duration substantially overlaps the first data enable duration.

Image adjusting apparatus and associated method

An apparatus and method for adjusting the pixel resolution of an input image is disclosed. According to the present invention, the pixel resolution of the input image is adjusted by oversampling an analog signal representative of the input image at a higher frequency than the pixel rate of the original image, then digitally downscaling to the desired horizontal resolution of an output image. The horizontally downscaled image is then stored in a buffer memory and subsequently scaled up to the desired vertical resolution of the output image. Preferably, oversampling of the analog signal is performed at a frequency that is an integer multiple of the input pixel rate, thus providing coherent sampling to help avoid aliasing artifacts in the sampled image.

Apparatus and method for increasing pixel resolution of image using coherent sampling

An image processing system includes a memory, a data slicer and an image processor. The data slicer divides each of current image data and adjacent image data into a first portion and a second portion to be stored into the memory. The image processor reads from the memory the first portion and the second portion of the current image data and the first portion of the adjacent image data for image processing.

Image processing system and image processing method

An overdriving apparatus is provided in the invention. The apparatus includes a receiving module, a storing module, a dynamic information generating module, and an image driving module. The receiving module receives image data relative to an image signal. The storing module is used for storing the image data. Based on the image data, the dynamic information generating module generates dynamic information corresponding to a current image. The image driving module then generates an overdriving signal and/or a standard driving signal, according to the dynamic information and the image data, to drive a display.

Method and apparatus for generating an overdrive signal for a liquid crystal display

An over-drive value generating apparatus applied to an LCD display includes a pixel value converting unit, a gain generating unit and a calculation unit. The pixel value converting unit generates a converted pixel according to a current pixel of a current image and a corresponding pixel of a previous image. The gain generating unit generates a gain according to a position of the current pixel. The calculation unit generates an output pixel according to the current pixel, the converted pixel and the gain.

Apparatus for generating over-drive values applied to LCD display and method thereof

A OSD management method for writing OSD data into a memory, the management method includes: respectively writing a first partial data and a second partial data of the first OSD data into a first memory space and a second memory space of the memory; and respectively writing a third partial data and a fourth partial data of the first OSD data into a third memory space and a fourth memory space of the memory; wherein the first and third memory space associate with a first row address of the memory, and the second and fourth memory space associate with a second row address of the memory.

Management method and display method of on-screen display thereof and related display controlling device

A video scaling apparatus includes a receiver for receiving incoming video signals having transmitted therein a plurality of incoming frames, each incoming frame having a first plurality of synchronization signals for indicating lines in the incoming frame; a scaler with a line extender for generating outgoing video signals having transmitted therein a plurality of outgoing frames, each outgoing frame having a second plurality of synchronization signals for indicating lines in the outgoing frame, and for generating an outgoing frame for each incoming frame. The line extender ensures durations of all lines in the outgoing video signals are of substantially equal length. By ensuring that all lines in the outgoing frame are of substantially the same length, the reliability of a display device receiving the outgoing video signals is increased. Additionally, the frequency requirements of an outgoing clock for the video signals can be less stringent.

Method of frame synchronization when scaling video and video scaling apparatus thereof

The present invention provides a display controller for scaling an input source image. The display controller dynamically adjusts the output clock so line buffer requirement is reduced to a minimum to balance input and output image timing for image scaling or non-scaling to destination devices. The present invention supports up-scaling and down-scaling or bypass. The blocks of the line buffer operates in a continuous and cyclical manner according to the status signal generated by the line buffer status detector and the output clock. As a result, any buffer overrun or underrun condition will be immediately corrected by the timing and therefore the number of blocks of line buffer are greatly reduced.

Display controller provided with dynamic output clock

A method and apparatus for automatically tuning the output line rate thereof and a display controller provided with the same. The display controller of the present invention provides a display controller having a line buffer, an input means, an output means, a status detector, and an auto-tune control means. The input means is employed to write line data into the line buffer at an input line rate, and the output means is employed to read the written line data from the line buffer at an output line rate. The status detector is coupled to the input means and the output means for generating a status signal indicating whether the input line rate and the output line rate are unbalanced. The auto-tune control means is used to adjust the output line rate in response to the status signal so as to balance the input line rate and the output line rate.

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Taoyuan, Taiwan

Jiunn-Kuang Chen