Advanced Semiconductor Engineering, Inc.

Jiunn Chen

Meng-Jen Wang

Tsung-Yueh Tsai

Yi-Shao Lai

Tsung-Hua Wu

Ming-Hsiang Cheng

Hsiao-Chuan Chang

Shyh-Ing Wu

Shih-Kuang Chen

Chueh-An Hsieh

Li-Cheng Tai

Tsung-Chieh Ho

Jui-I Yu

A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.

Semiconductor device package having a jumper chip and method of fabricating the same

A recyclable stamp device and a recyclable stamp process for wafer bond are provided. The recyclable stamp device includes a substrate, a protective layer, a stack film structure and a cap. The protective layer is disposed on the substrate. An opening is positioned at the substrate and the protective layer to expose the substrate. The stack film structure includes an adhesion layer, a stress control layer and a wafer bond alignment mark layer. The adhesion layer is disposed on the protective layer and the exposed substrate. The stress control layer is disposed on the adhesion layer. The wafer bond alignment mark layer is disposed on the stress control layer. The wafer bond alignment mark layer includes an alignment mark at a side of the opening. The cap has a capping portion disposed on the wafer bond alignment mark layer corresponding to the opening.

Recyclable stamp device and recyclable stamp process for wafer bond

A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.

Wafer structure with a multi-layer barrier in an UBM layer network device with power supply

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Kaohsiung, Taiwan

Jiunn Chen