Taiwan Semiconductor Manufacturing Comp. Ltd.

Jiun-Yu Tsai

Hung-Cho Wang

Ming-Che Ku

Harry-Hak-Lay Chuang

Sheng-Huang Huang

Jun-Yao Chen

A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.

Magnetic random access memory device and formation method thereof

A method of forming a MRAM device includes forming an interconnect structure spanning a memory region and a peripheral region; forming a MTJ stack over the interconnect structure within the memory region; depositing a dielectric layer over the MTJ stack and spanning the memory region and the peripheral region; removing a first portion of the dielectric layer from the peripheral region, while leaving a second portion of the dielectric layer within the memory region; after removing the first portion of the dielectric layer from the peripheral region, forming a first IMD layer spanning the memory region and the peripheral region; forming a dual damascene structure through the first IMD layer to a metallization pattern of the interconnect structure within the peripheral region; and after forming the dual damascene structure within the peripheral region, forming a top electrode via in contact with a top electrode of the MTJ stack.

A method for fabricating an integrated circuit is provided. The method includes forming a memory cell over a substrate, wherein the memory cell comprising a top electrode, a bottom electrode, and a resistance switching element between the bottom electrode and the top electrode; forming a dielectric layer over the memory cell and the substrate; etching a via opening in the dielectric layer to expose the top electrode of the memory cell; forming a spacer in the via opening; performing a liner removal process to the dielectric layer after forming the spacer; and forming a conductive feature connected to the top electrode in the via opening.

Growing community of inventors

Hsinchu, Taiwan

Jiun-Yu Tsai