Taiwan Semiconductor Manufacturing Comp. Ltd.

Jiun-Wei Lu

Jiann-Tyng Tzeng

Wei-Cheng Lin

Shih-Wei Peng

Kam-Tou Sio

Te-Hsin Chiu

Te-hsin Chiu

An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Backside conductive segments cover a first active region and define an opening above a second active region

Integrated circuit with frontside and backside conductive layers and exposed backside substrate

An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

Integrated circuit including back side conductive lines for clock signals

An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

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Keelung, Taiwan

Jiun-Wei Lu