National Chung Cheng University

Other

Jiun-In Guo

Jinn-Shyan Wang

Jia-Wei Chen

Ching-Lung Su

Kuan-Hung Chen

Chih-Hao Chang

Yao-Chang Yang

Jui-Sheng Lee

Jeng-Wei Liao

Cheng-An Chien

Chun-Hao Chang

Yi-Huan Ou Yang

Chia-Jui Huang

Jia-Hou Chang

Chien-Chang Lin

Yao Li

Cheng-Yen Chang

Chih-Ta Chien

A view synthesis method of depth mismatching checking and depth error compensation, wherein, input left and right maps are warped in a processor to perform view synthesis, comprising following steps: when a present pixel moves to a position of a target pixel after warping, compute respectively pixel displacement amounts for said present pixel to move to said target pixel in said left and said right maps, to figure out coordinate of said target pixel; determine if depth value of the present pixel is greater than that of said target pixel, if an answer is positive, determine if depth value of said present pixel matches that of coordinate adjacent to said target pixel; and if answer is negative, set depth value of said target pixel to a hole; otherwise, cover said target pixel with pixel value of said present pixel, hereby completing refining even minute errors.

View synthesis method capable of depth mismatching checking and depth error compensation

A low-complexity method of converting 2D images/videos into 3D ones includes the steps of identifying whether each pixel in one of the frames is an edge feature point; locating at least two vanishing lines in the frame according to the edge feature point; categorizing the frame into the one of close-up photographic feature, of landscape feature, and of vanishing-area feature; if the frame is identified to have the vanishing-area feature or the landscape feature to generate a GDM; and apply a modificatory procedure to the GDM to generate a final depth information map; if the frame is identified to have the close-up photographic feature, distinguish between a foreground object and a background information in the frame and define the depth of field to generate the final depth information map.

Low-complexity method of converting image/video into 3D from 2D

A predictive coding method for coding intra of frames is revealed. Firstly, an encoder divides an image frame into a plurality of macroblocks. Then the encoder sets predictive coding models corresponding to these macroblocks according to a ratio. The encoder performs predictive coding for coding each macroblock according to the corresponding predictive coding model so as to get and output a coded image. By the present invention, various predictive coding models are set and applied to code the different macroblocks so as to increase predictive coding efficiency. The intra prediction efficiency and image compression efficiency are improved simultaneously.

Predictive coding method for coding texture of image

A method for reducing computational complexity of video compression standard is provided, and it includes an intra 4&#xd7;4 macroblock (I4MB) search algorithm, an intra 16&#xd7;16 macroblock (I16MB) search algorithm and a chroma search algorithm. The I4MB search algorithm and I16MB search algorithm accelerate the prediction process of the luma macroblock, and the chroma search algorithm accelerates the prediction process of chroma macroblock. The above algorithms can greatly reduce the computation of prediction mode of video compression standard.

Method for reducing computational complexity of video compression standard

An intra prediction circuit device applied to the H.264 video coding standard is provided. The intra prediction device uses a method of decreasing the repeated operations of the shared terms of the video pixel data to reduce the circuit computation and simplify the hardware architecture. In the intra prediction scheme, the computational complexity can be lessened by implementing not only the adder based method but also decomposition technique to simplify the algorithm of the intra prediction.

Intra prediction circuit device applied to the H.264 video coding standard

A multimedia coding system has different picture qualities with different coding characteristics. It is done through a scaleable fractional motion estimation (FME) in H.264 and a block size trend prediction FME. Three quality levels are thus obtained. The first level processes a complete calculation and obtains a best picture; the second level, fewer calculation with a low power consumption and an acceptable picture quality; and the third level, fewest calculation with a fastest speed. And the present invention is suitable for hardware design to obtain a high efficiency, a low cost and a high performance.

Method of scalable fractional motion estimation for multimedia coding system

Design techniques and their circuit designs for versatile and scalable video coding are proposed, in which the inner product operation in the transform coding expression is taken apart into a series of add and shift operations, and the expression is partitioned into several sub-expressions. Taking each order of the add-and-shift series as a clock period, several adders/subtractors and a shift accumulator are used to carry out corresponding additions/subtractions and shift operations to finish the inner product operations. The calculating result is accumulated until all the orders are finished. The final accumulated value is the output of the transform coding. Data throughput rate can thus be enhanced to save the power consumption of the circuit system. Moreover, a dynamic guarded computation method and a switching power suppression technique are provided to further lower the power consumption.

Design techniques and their circuit designs for versatile and scalable video coding

A method for memory controlling is disclosed. It includes an embedded address generator and a controlling scheme of burst terminates burst, which could erase the latency caused by bus interface during the access of non-continuous addresses. Moreover, it includes a controlling scheme of anticipative row activating, which could reduce the latency across different rows of memory by data access. The method could improve the access efficiency and power consumption of memory.

Memory controlling method

A device for video decoding is disclosed. It includes at least a pipeline scheduler, a decoding core, a segmented context memory and a context cache. The pipeline scheduler and the decoding core could decrease the time taken in a code-decoding period. The segmented context memory and the context cache could reduce accessing time of reading and writing context values.

Growing community of inventors

Chia-Yi, Taiwan

Jiun-In Guo