Integrated Device Technology, Inc.

Jitesh Shah

David J Pilling

Ajay Kumar Ghai

Viresh Patel

Robert A Gubser

Kenneth Astrof

Derek Huang

Camille Kokozaki

Errol Monsale

Diane Peng

A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess therein that is at least partially lined with at least one segment of an inductor. This inductor may be electrically coupled to an electrical component within the integrated circuit substrate. In some embodiments, the inductor is patterned to extend along a sidewall and interior top surface of the recess, which extends opposite the integrated circuit substrate. The inductor may include a plurality of arcuate-shaped segments and may be patterned to be symmetric about a center-tapped portion thereof. The cap may also include a magnetic material therein that increases an effective inductance of the inductor relative to an otherwise equivalent cap and inductor combination that is devoid of the magnetic material.

Packaged integrated circuits having high-Q inductors therein and methods of forming same

An integrated circuit () that is electrically connected to a printed circuit board () with a package substrate () includes a circuit body (), and a bump array () that electrically connects the circuit body () to the package substrate (). The bump array () includes a first bump set () having a plurality of signal bumps () and a plurality of non-signal bumps () alternatingly interspersed and aligned along an axis. With the present design, the bump array () allows each signal bump () to be surrounded by a power bump () and a ground bump (). The package substrate () includes (i) a package body (); and (ii) a pin array () that includes a first pin set () that includes a plurality of signal pins () and a plurality of non-signal pins () alternatingly interspersed and aligned along an axis.

Flip chip bump array with superior signal performance

A test assembly () for testing a device () having a heat spreader (), a package substrate () having a substrate ground (G), and a grounding conductive segment (A), includes (i) an input conductive segment () that is electrically connected to the heat spreader (), (ii) a test board () having a board ground (), and (iii) a control system () that is electrically coupled to the input conductive segment () and the board ground (). During testing, the device () is positioned so that the substrate ground (G) is electrically connected to the board ground (). Additionally, the control system () directs a test current to one of the input conductive segment () and the board ground () to test the effectiveness of the grounding conductive segment (A) including a first electrical interface (A).

Test assembly for verifying heat spreader grounding in a production test

A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires.

Lead frame package

A package () for electrically connecting an integrated circuit () to a printed circuit board () includes a mount array () and a substrate body (A). The mount array () is electrically connected to the integrated circuit (). The mount array () includes a plurality of positive terminal mounts (), a plurality of negative terminal mounts (), and a plurality of signal mounts (). The substrate body (A) includes a first conductive layer (), a second conductive layer (), and an insulating layer () that is positioned between the first conductive layer () and the second conductive layer (). The first conductive layer () includes (i) a terminal portion () that is connected one of the terminal mounts () (), and (ii) a signal portion () that is connected to the signal mounts (). Further, the second conductive layer () is directly connected to the other of the terminal mounts () (). Additionally, the package () can include a capacitor () having a positive capacitor pad () and a negative capacitor pad (). The electrical path of the capacitor () to the mount array () in the designs provided herein is relatively short, has relatively low impedance, and has a relatively low loop inductance.

Package with improved connection of a decoupling capacitor

A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages.

Multi-package slot array

A package substrate () for electrically connecting an integrated circuit () to a printed circuit board () includes a core (), a patterned conductive layer (), a plurality of spaced apart, discrete capacitors (), and an insulating layer (). The patterned conductive layer () is positioned on the core (). The discrete capacitors () are electrically connected to the patterned conductive layer (). The insulating layer () covers the patterned conductive layer () and separates the capacitors (). The capacitors () are positioned to provide a relatively low impedance path for quick access to power to stabilize the voltage delivered to the integrated circuit (), and the capacitors () do not occupy valuable space on the integrated circuit (), and the printed circuit board (). Further, this placement of the capacitor assembly () allows for use of a relatively large number of discrete capacitors () without taking up valuable space from the surface of the package substrate ().

Package substrate with inserted discrete capacitors

A package for a flip-chip integrated circuit device and a packaged flip-chip integrated circuit device that include ground strips and power strips disposed on the top surface of the package substrate. Decoupling capacitors are disposed over and electrically coupled to a ground strip and are disposed over and electrically coupled to a power strip. Microvias electrically couple the power strips to a power plane and electrically couple the ground strip to a ground plane. Each power strip and ground strip extend within a die attach region of the package substrate such that a semiconductor die can be bonded thereto for coupling power and ground between the semiconductor die and the decoupling capacitors. The power strip and ground strip provide low impedance pathways between the flip-chip semiconductor die and the decoupling capacitors. Thereby, effective decoupling capacitance is provided that is suitable for high frequency applications.

Method and apparatus with power and ground strips for connecting to decoupling capacitors

A micro leadframe package and a method for forming a micro leadframe package are disclosed in which two leadframes that include paddles are coupled together such that only dielectric material extends between the two paddles. Semiconductor die are attached to paddles on the top leadframe, and a wire bonding process is then performed, followed by a molding process, plating, and a singulation process. This forms a micro leadframe package that, when ground is coupled to one paddle and power is coupled to the other paddle, provides a low inductance path for both power and ground supply to the semiconductor die. Moreover, as only dielectric material extends between the two paddles, the two paddles and the dielectric material that extends between the paddles form a capacitor, providing decoupling capacitance within the micro leadframe package.

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Fremont, CA, United States of America

Jitesh Shah