National Semiconductor Corporation

Astera Labs, Inc.

Texas Instruments Corporation

Asiera Labs, Inc.

Jitendra Mohan

Enrique Musoll

Ken (Keqin) Han

Subbarao Arumilli

Pulkit Khandelwal

Casey Morrison

Vivek Trivedi

Chi Feng

Vikas Khandelwal

Charan Enugala

Ramsin Michael Ziazadeh

Devnath Varadarajan

Arlo Jame Aude

Yongseon Koh

Abu-Hena Mostafa Kamal

Luu Thanh Nguyen

Laurence Douglas Lewicki

Vijaya G Ceekala

Ivan Duzevik

Gary A Brown

William Paul Mazotti

Bruce Carlton Roberts

Jia Liu

Neeraj Anil Pendse

John Andrew Campbell

Anh T Tran

James B Wieser

Alan Erik Segervall

Varadarajan Devnath

Khaldoon S Abugharbieh

Stephen Gee

Justina Provine

Quyet Nguyen

Vjay Ceekala

A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Low-latency retimer with seamless clock switchover

A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Virtual metadata storage

A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Low-latency signaling-link retimer

Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Configurable-aggregation retimer with media-dedicated controllers

A system and method is disclosed for adding a low data rate data channel to a 100Base-T Ethernet link without significantly impacting an IEEE defined 100Base-T protocol for the Ethernet link. A dual data channel transmitter encodes a high data rate data stream in an MLT-3 encoder and encodes a low data rate data stream using bit representations that are not valid bit representations in the MLT-3 encoder. The dual data channel transmitter transmits both of the encoded bit streams in a dual data stream. A dual data channel receiver receives the dual data stream and separates and decodes the two bit streams. A low data rate data channel is provided in conjunction with a high data rate data channel without significantly impacting the operation of the high data rate data channel.

System and method for adding a low data rate data channel to a 100Base-T ethernet link

A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.

Low voltage differential signal driver with reduced power consumption

A system and method is disclosed for providing a strobed comparator with reduced offset and reduced charge kickback. The strobed comparator circuit comprises a differential pair of transistors coupled to a first switch circuit, a regenerative latch circuit, a first strobe signal line coupled to the switch circuit and a second strobe signal line coupled to the regenerative latch circuit. The first and second strobe signal lines provide separate strobe controls. The differential pair of transistors reduces the charge kickback effect by remaining in an 'on' state. The differential pair of transistors is enabled when the regenerative latch circuit is in a reset condition and the regenerative latch circuit is enabled when the differential pair of transistors is in a saturation condition.

System and method for providing a strobed comparator with reduced offset and reduced charge kickback

A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation current source, and an output tracking circuit. The bias current source is operable to generate a bias current and an output voltage for the VCSEL and to generate a replica output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The output tracking circuit is coupled to the bias current source. The output tracking circuit is operable to generate a feedback signal for the bias current source based on the output voltage and the replica output voltage. The bias current source is also operable to generate the output voltage and the replica output voltage based on the feedback signal.

Driver for vertical-cavity surface-emitting laser and method

A slow monitor diode having a bandwidth only partially overlapping a lower end of a data transmission spectrum for a data transmission laser is employed to detect and control average output power of the data transmission laser and, from peak-to-peak measurements, optical modulation amplitude. The output current from the monitor diode reaches a peak value for long runs of consecutive logical 1's or 0's. Using peak detectors with a long decay rate, the peak-to-peak signal amplitude, directly representative of optical modulation amplitude, may be determined.

Method of using low bandwidth sensor for measuring high frequency AC modulation amplitude

An apparatus, device, and method for loss of signal detection in a receiver are provided. A reference circuit is operable to rectify a reference signal. An input circuit is operable to rectify an input signal. A comparator is operable to compare outputs of the reference circuit and the input circuit and to generate an output signal based on the comparison. The output signal indicates whether the input signal falls within threshold limits defined by the reference signal. A second reference circuit and a second input circuit could also be used, and the reference circuits and input circuits can be selectively enabled and disabled based on which of multiple differential pairs is enabled in a receiver receiving the input signal. The differential pairs can be used in the receiver to generate an output signal based on the input signal.

Apparatus and method for loss of signal detection in a receiver

An apparatus, device, and method for high-speed serial communications are provided. An input circuit is operable to receive an input signal, where the input circuit includes transistors forming (i) a first differential pair associated with a first current source and (ii) a second differential pair associated with a second current source. An output circuit is coupled to the input circuit and is operable to generate an output signal based on the input signal. A sensing circuit is operable to estimate a voltage associated with one of the current sources. A comparator is operable to compare the estimated voltage and a reference voltage and to selectively enable one of the differential pairs and disable another of the differential pairs based on the comparison. The differential pairs could be enabled and disabled using a first switch associated with the first differential pair and a second switch associated with the second differential pair.

Apparatus and method for high-speed serial communications

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Santa Clara, CA, United States of America

Jitendra Mohan