Xilinx, Inc.

Jitendra Kumar Yadav

Santosh Yachareni

Kumar Rahul

Teja Masina

Md Nadeem Iqbal

Sourabh Swarnkar

Suresh Babu Kotha

A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

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Hyderabad Telangana, India

Jitendra Kumar Yadav