Cadence Design Systems, Inc.

Jitendra Kumar Yadav

Hari Anand Ravi

Vinod Kumar

Thomas Evan Wilson

Sachin Ramesh Gugwad

Hajee Mohammed Shuaeb Fazeel

Prakash Kumar Lenka

Sumit Gupta

Virvasav Sinha

Rajashekhar Krishnamurthy Rao

Embodiments included herein are directed towards a ring voltage-controlled oscillator based phase locked loop circuit. Embodiments may include an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations and a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit. Embodiments may further include a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture

A high-speed clocking circuit may include a single path digitally controlled coarse delay line including multiple stages. Each of the multiple stages may include a plurality of inverters and a logic gate electrically connected in series that are configured to enable a forward path of the single path digitally controlled coarse delay line prior to disabling a return path of the single path digitally controlled coarse delay line to minimize glitching.

Efficient clocking structures for high-speed systems using hybrid digital delay lanes

Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

Read data strobe path having variation compensation and delay lines

The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

Clock duty cycle measurement

The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.

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Bengaluru, India

Jitendra Kumar Yadav