Arm Limited

Jitendra Dasani

Shri Sagar Dwivedi

Vivek Nautiyal

Fakhruddin Ali Bohra

Lalit Gupta

Satinderjit Singh

Andy Wangkun Chen

Bo Zheng

Vivek Asthana

Akshay Kumar

Abhishek B Akkur

Gaurav Rattan Singla

Vikash

Rajiv Kumar Sisodia

Jungtae Kwon

Amit Chhabra

Navin Agarwal

Akash Bangalore Srinivasa

Yicong Li

Manoj Puthan Purayil

Vasimraja Bhavikatti

Daksheshkumar Maganbhai Malaviya

Sujit Kumar Rout

Sharryl Renee Dettmer

Yeon Jun Park

Arjunesh Namboothiri Madhavan

A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

Dummy bitline circuitry

Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Write assist circuitry

Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

Integrated circuit using discharging circuitries for bit lines

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

Fault detection circuitry

Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

Routing structures for memory applications

Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

Providing a discharge boundary using bitline discharge control circuitry for an integrated circuit

Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

Transition coupling circuitry for memory applications

Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

High-speed memory architecture

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Power-on-reset circuit

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

Dummy wordline tracking circuitry

Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

Bitline write assist circuitry

A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

Skewed corner tracking for memory write operations

Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

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Cupertino, CA, United States of America

Jitendra Dasani