Samsung Electronics Co., Ltd.

JiSun Hong

Taehun Kim

Se-Ho You

Byungmoon Bae

JinGyu Kim

Un-Byoung Kang

Jongbo Shim

Hyuekjae Lee

Hyunki Kim

Kyoungsei Choi

Taeje Cho

SeokWon Lee

Youngbok Kim

Hyung-sun Jang

A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

Package substrates

A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.

Semiconductor device and method of manufacturing the same

Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.

Method for wafer level package and semiconductor device fabricated using the same

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Asan-si, South Korea

JiSun Hong