Nippon Telegraph and Telephone Corporation

Jirou Naganuma

Atsushi Sagata

Koyo Nitta

Hiroe Iwasaki

Mitsuo Ikeda

Hiroaki Matsuda

A video signal generation apparatus for decoding a bit stream to generate a video signal, includes: a writing unit configured to write a flag value indicating whether a decoding target block has been coded by intra-coding or inter-coding in a specified bit position on one bit plane having a size the same as that of the decoding target block, to write information indicating a coding division form of the decoding target block in a specified common area on the one bit plane, and to write the coding information in a specified switch interpretation area on the one bit plane according to a data format conforming to the intra-coding if the decoding target block has been coded by intra-coding, and to write the coding information in the specified switch interpretation area according to a data format conforming to the inter-coding if the decoding target block has been coded by inter-coding; and a generation unit configured to generate a video signal by superimposing the one bit plane on a decoded image of the decoding target block.

Video signal generation apparatus, video signal generation method, video signal generation program, and computer readable recording medium recording the program

In motion search using a PE array, a technique is provided for enabling high-speed calculation while avoiding bank conflict without increasing a memory for storing pixels outside the screen. When pieces of pixel data of a plurality of lines to be read from the memory(reference image memory) exist in a same bank, the conflict bank anticipatory read control unitreads pixel data of a line in advance, and a read data holding circuitholds the data until timing for inputting to a PE array unit. Accordingly, bank conflict can be avoided when reading pixel data from the memory, so that smooth pipeline processing by the PE array unitcan be realized.

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Yokosuka, Japan

Jirou Naganuma