Nec Corporation

Nippon Electric Co., Ltd.

Jiroh Shimada

Hiroshi Morito

Hiroshi Iguchi

Youichi Miyagawa

A coincidence decision circuit includes a plurality of data inputs and at least one coincidence decision output. This circuit comprises a plurality of coincidence detection circuit each having a plurality of inputs connected to a corresponding number of data inputs selected from the data inputs of the circuit. Each of the coincidence detection circuit is selectively put in an operable condition in response to a given selection signal so as to generate an coincidence detection signal. A circuit is connected to the coincidence detection circuit to respond to a timing signal to read out the coincidence detection signal from the coincidence detection circuit put in the operable condition. Further, another circuit is connected to the read out circuit to output the coincidence detection signal at a predetermined timing.

Coincidence decision circuit composed of MOS OR gate array and MOS AND

A half adder includes a first drive stage having an input and connected at its output a carry output and a second drive stage having an input and connected at its output to an addition data output. Further, a circuit is provided to precharge the inputs and the outputs of the first and second drive stages at a first timing so as to put these drive stages in a first logic condition, and then to put these drive stages in an operable condition at a second timing later than the first timing. A first logic stage is connected to a data input and a carry input, respectively, so as to generate a first logical signal to the inputs of the first and second drive stages, when the data input and the carry input assume a first logic level, thereby to put the drive stages in a second logic condition opposite to the first logic condition. Futhermore, a second logic stage is connected to the output of the second drive stage and having inputs connected to the data input and the carry input, respectively. This second logic stage is adapted to forcedly change the logic level of the second drive stage output when the data input and the carry input assume a second logic level opposite to the second logic level and at a third timing later than the second timing.

Half adder having a pair of precharged stages

An error signal generator for generating a plurality of error signals for various control values, comprises a time controller for sequentially and periodically generating a plurality of status signals, the number of which corresponds to the number of the control values. A read-out signal generator receives reference signals and/or detection signals for generating a read-out signal in response to one of the reference signals selected by the associated status signal. There is provided a preset memory storing a plurality of preset digital values for the control values and responsive to the read-out signal so as to output to a bus the preset digital value designated by the associated status signal. A count memory responds to each status signal so as to read out the data to the bus from one of the memory areas designated by the associated status signal and then is rewritten with the data on the bus into the same memory area. An adder operates to periodically subtract a value of '1' from the data on the bus and to return the result of the subtraction to the bus. An error memory responds to each of the detection signals so as to write the data on the bus into one of the memory areas designated by the associated status signal. The respective memory areas provide the data stored therein as the error signals.

Error signal generator

A circuit for comparing first and second binary coded digital data signals has a plurality of first circuits each including first and second transistors of a P-channel type connected in series between a first potential terminal and a first output node, a plurality of second circuits each including third and fourth transistors of an N-channel type connected in series between a second potential terminal and a second output node, and means for precharging the first and second output nodes to first and second logic levels, respectively. The first and third transistors are supplied with one bit data of the first signal, and the second and fourth transistors are supplied with an inverted data of the second signal. A change in the logic level at least one of the first and second output nodes is detected.

Data comparison circuit constructed with smaller number of transistors

An improved oscillator circuit utilizes an inverter which includes a pair of series connected MOS-FETs of differing conductivity types. A switching circuit is operable to supply the gate bias voltages from one of two separate sources, one of which is used during periods of start-up or unstable oscillation to decrease start-up time, and the other of which is used during periods of stable oscillation to decrease current consumption.

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Tokyo, Japan

Jiroh Shimada