Matsushita Electric Industrial Co., Ltd.

Nuvoton Technology Corporation Japan

Panasonic Corporation

Jiro Miyake

Tamotsu Nishiyama

Kazuki Ninomiya

Katsuya Hasegawa

Naohisa Hatani

Shintaro Tsubata

Miki Urano

Masaya Sumita

Hiroshi Kadota

Ichiro Okabayashi

Toshinori Maeda

Tadashi Okamoto

Keizo Sumida

Toru Morikawa

Genichiro Inoue

Tomoharu Kawada

Masao Inoue

Shinobu Kanda

Midori Takahashi

Hiroyuki Mizohata

Gary Brown

Yoshinori Maeda

A voltage measurement device includes: a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a device address generating circuit which generates a device address according to a first address assignment command received from a preceding voltage detection circuit located at a preceding stage; and an address assignment command generating circuit which generates a second address assignment command according to the first address assignment command, and sends the second address assignment command to a next voltage detection circuit located at a next stage.

Voltage measurement device, voltage detection circuit, and device address generation method

A voltage measurement device is a voltage measurement device including a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a communication end information holding circuit which holds communication end information specifying, as at least one communication end position, at least one of the plurality of voltage detection circuits; and a communication control circuit which controls transfer for sending a communication command received from a preceding voltage detection circuit located at a preceding stage to a next voltage detection circuit located at a next stage, according to the communication end information.

Voltage measurement device, voltage detection circuit, and voltage detection method

When an interruption instruction occurs in an information processing apparatus including a CPU and a coprocessor, execution of a single dedicated instruction 'GETACX Dm,Dn' performs saving of necessary data from all registers. 'Dm' is a value output from a general register groupto a first data input bus. Each of calculation units implemented in a coprocessorrecognizes a value stored therein. If a value &#x201c;Dm&#x201d; specifies one of the calculation units, the specified calculation unit outputs, to a selector, data stored in a register included in the specified calculation unit. An implemented calculation unit information output circuitstores therein the count of the calculation units implemented in the coprocessor. If a value of the first data input busis greater than the count of the calculation units, the implemented calculation unit information output circuitoutputs a value &#x201c;1&#x201d; to a flag register. Based on the fact that the value stored on the flag registeris &#x201c;1&#x201d;, a CPUrecognizes that saving of the data from the register has been completed.

Processing system having co-processor for storing data

In order to acquire answer information to be searched from a large amount of question information, there is provided an FAQ search engine which can acquire an appropriate term and acquire appropriate information by using the term as a search keyword. It comprises a document of describing a search keyword, a terminal unit for acquiring the search keyword from the document and inputting the search keyword, a database which has a keyword group consisting of search keywords obtained by adding numbers to the keywords described in the document, and an FAQ data group for managing FAQ data relevant to the numbers, a number acquisition portion for acquiring the number corresponding to the provided search keyword out of the keyword group, a data extract portion for acquiring FAQ data corresponding to the number acquired from the number acquisition portion out of the FAQ data group, and an FAQ display portion for displaying the FAQ data on the terminal unit.

FAQ search engine

To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal processor is provided with an instruction decoder, a control selecting circuit, a selecting circuit and an arithmetic unit. The instruction decoder decodes an instruction to output two control signals. The control selecting circuit is connected to the instruction decoder and selects one of the control signals in accordance with a flag signal stored in a flag holding circuit to output the selected signal. The selecting circuit selects one of a plurality of input data in accordance with the control signal outputted by the control selecting circuit and outputs the selected data. The arithmetic unit performs an operation on the data outputted by the selecting circuit.

Signal processor for performing conditional operation

According to the signal processing method of the invention, control data is previously generated by using the name of a control signal included in an object signal, and then, the object signal including the control signal is input. The name of the control signal in the control data is substituted with the content of the control signal included in the object signal, and then the object signal is processed by a signal processing unit by using the control data including the content of the control signal. Therefore, the signal processing unit can change the processing to be performed on the object signal in accordance with the content of the control signal included in the object signal.

Development supporting method and device for signal processing system

A plurality of processing elements are connected in cascade so as to constitute a single signal processing apparatus. The signal processing apparatus has a first path for transferring an input data signal and a second path for transferring a processing result of the input data signal. Each of the processing elements has a first input disposed on the first path, a data holding circuit for holding the data signal supplied through the first input, a product-sum circuit for executing a product-sum operation between the data signal held in the data holding circuit and another data signal, a second input disposed on the second path so as to supply the other data signal to the product-sum circuit, a result register for holding the result of the operation calculated by the product-sum circuit and supplying the held result of the operation to the second path, an output selecting circuit for supplying either one of the data signal held in the data holding circuit and the result of the operation held in the result register, and a processing control circuit for controlling respective operations of the data holding circuit, product-sum circuit, result register, and output selecting circuit. Since a route extending from the result register to the output selecting circuit forms a bypass from the second path to the first path, a flexible process can be performed by the signal processing apparatus by using or not using the bypass depending on control information.

Processing elements connected in cascade having a controllable bypass

A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.

Signal processor

In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected. As a result of such arrangement, a single piece of image processing hardware can be shared between different broadcasting systems as well as between different algorithms.

Signal processor capable of sharing common hardware in a plural

A duty ratio-guaranteed reference clock signal and a duty ratio-unguaranteed drive clock signal serve as input to a clock signal waveform-correcting system in accordance with this invention. The system thereafter puts out a post-correction drive clock signal that is duty ratio-guaranteed. The system has a phase comparator and a switch circuit. The phase comparator puts out a HIGH signal as long as the reference clock signal and the drive clock signal disagree in logical level. The switch circuit transmits an inverted signal as a result of inverting the drive clock signal, to an output signal of a first buffer to which the drive clock signal is applied. A second buffer takes in the output signal and puts out a post-correction drive clock signal.

Method and system for clock-signal waveform correction

A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Processing of pixel data at an operating frequency higher than the

An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E�(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E�x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E�x-1,y! arithmetic cell via a direct bus as well as from an E�x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

This invention discloses an improved signal processor comprising first to third arithmetic units forming a pipeline structure, first to third control information hold circuits each of which holds control information for its corresponding arithmetic unit, first to third selection circuits, and first to third signal transfer circuits. Transfer of a selection signal is delayed by a proportional interval of time to the processing time of each arithmetic unit. In order to perform the switching of arithmetical operations in each arithmetic unit according to the data flow in the pipeline processing, each selection circuit selects among the control information hold circuits depending on the selection signal transferred and provides control information held in a selected control information hold circuit to a corresponding arithmetic unit.

Pipeline signal processor

The present invention discloses a 2-way set-associative cache memory incorporating thereinto a write buffer. Tag entries corresponding to data entries within each bank are added valid bits and write reserve bits. The write reserve bit is set when a write request occurs and is reset when the requested write operation is completed. When a cache miss occurs, a replacement controller selects one of two data entries as a candidate for replacement (i.e., a data entry to which a corresponding write reserve bit is not set).

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Osaka, Japan

Jiro Miyake