Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Jiro Matsufusa

Hiroaki Nishimura

Takeshi Kishida

Tomoharu Mametani

Yukihiro Nagai

Akinori Kinugasa

Shigenori Kido

Yoji Nakata

Tadashi Nishimura

Takahisa Eimori

Toshiyuki Oashi

In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Semiconductor device having a potential fuse, and method of manufacturing the same

A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

Semiconductor device having test mark

A memory cell has a cylindrical electrode having a porous cylindrical portion, and insulating layers for making less steep the height of cylindrical electrode are provided in the peripheral circuit region. Thus a semiconductor memory device and manufacturing method thereof can be provided in which the step between the memory cell array region and the peripheral circuit region can be made less steep by a smaller number of manufacturing steps.

Semiconductor memory device and manufacturing method thereof

Semiconductor memory cell with porous cylindrical electrode

A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film ( ) formed of p-TEOS is deposited to cover a substrate ( ) and wires ( ) formed on the substrate ( ). A second insulation film ( ) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate ( ); therefore, the second insulation film ( ) is etched. The etching is stopped at the point where the surface ( ) of the first insulation film ( ) on the wires ( ) is exposed. This ensures good surface,planarity. A third insulation film ( ) is stacked on top of the second insulation film ( ), and portions of the third insulation film ( ) above the wires ( ) are isotropically etched to form openings ( ). At this time, the isotropic etching does not extend over the second insulation film ( ).

Method of manufacturing contact structure

Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (,) in which impurity is diffused is deposited on the entire surface including the inside of a hole (,A). An etching process of the polysilicon layer (,) is performed to form a storage node electrode composed of the polysilicon layer (,) remaining on the bottom and side of a groove for metallization (,) and in the hole (,A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (,), and a plug part disposed in the hole (,A). The storage node electrode is electrically connected via the plug part to a diffused region (,) of a semiconductor substrate (,).

Method of manufacturing semiconductor device

In order to correspond to high integration with large capacity of a semiconductor device, provided are a structure of the semiconductor device and a method for manufacturing the same in which a horizontal dimension can be reduced in either a memory cell region or a region where a peripheral circuit is to be formed or both the regions. A TFT is superposed on a trench capacitor with an insulation film provided therebetween in a DRAM memory cell region, and a TFT is superposed on a bulk transistor with an insulation film provided therebetween in a region where a peripheral circuit is to be formed. Consequently, elements are arranged three-dimensionally. Thus, a horizontal dimension of a region where each element is to be formed can be reduced.

DRAM memory with TFT superposed on a trench capacitor

A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.

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Tokyo, Japan

Jiro Matsufusa