Intel Corporation

Jiro Kubota

Kinya Ichikawa

Shawna M Liff

Omkar G Karhade

Nitin A Deshpande

Yoshihiro Tomita

Takashi Kumamoto

Shuji Inoue

Yohko Mashimoto

Masayuki Akiba

Mashahiro Kuroda

Kenji Takahashi

A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

Picture frame stiffeners for microelectronic packages

Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

Encapsulated stack of dice and support therefor

Encapsulation of a stack of semiconductor dice

A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

Fluxless flip chip interconnection

An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.

Method for producing a multilayer interconnection structure

Multiregion solder interconnection structure

Growing community of inventors

Tsukuba, Japan

Jiro Kubota