Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Shanghai Hua Hong Nec Electronics Company, Limited

Semiconductor Manufacturing (shanghai) International Corporation

Semiconductor Manufacturing (beijing) International Corporation

Jiquan Liu

Ming Zhou

Shengan Xiao

Wei Ji

Charles Chao Wang

Changzhou Wang

Xuan Xie

Liang Yao

Yuanyuan Yu

Semiconductor structure and method for forming semiconductor structure are provided. A substrate is provided, including a first dielectric layer, a first conductive layer and a second conductive layer. A first stop layer is formed on a top surface of the first conductive layer and a top surface of the second conductive layer, and a second stop layer is formed on a surface of the first dielectric layer. A second dielectric layer is formed on a surface of the first stop layer and a surface of the second stop layer. A first opening and a second opening are formed in the second dielectric layer by etching a portion of the second dielectric layer until the surface of the first stop layer is exposed. The first opening exposes the first stop layer on the first conductive layer, and the second opening exposes the first stop layer on the second conductive layer.

Semiconductor structure and forming method thereof

A semiconductor device and its manufacturing method are presented, relating to semiconductor technology. The manufacturing method comprises: providing a substrate structure comprising a substrate, a source region on the substrate, and a gate structure on the source region; forming cavities on two opposing sides of the gate structure; epitaxially growing electrodes in the cavities, with each electrode comprising an electrode body and an amorphous layer on the electrode body; forming an dielectric layer on the substrate structure covering the electrodes and the gate structure; etching the dielectric layer to form a contact hole exposing the amorphous layer; forming a conductive adhesive layer on the bottom and on the side of the contact hole; and forming a contact component on the conductive adhesive layer filling the contact hole. In this semiconductor device, the adhesive layer may be directly formed on the amorphous layer, resulting in improved performance of the device.

Semiconductor device and manufacture thereof

A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: This semiconductor interconnect structure provides improved reliability over conventional structures.

Semiconductor interconnect structure and manufacturing method thereof

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.

Method for reducing via RC delay

The present disclosure discloses a resistive random access memory (RRAM) and a method for manufacture the RRAM. The method includes: providing a bottom interconnection layer; forming a bottom dielectric layer above the bottom interconnection layer, the bottom dielectric layer comprising a via through the bottom dielectric layer that exposes a portion of the bottom interconnection layer; and forming a bottom electrode layer in the via, the bottom electrode layer including a first electrode selectively grown above the bottom interconnection layer. The bottom electrode layer manufactured in such a way provides improved filling capability of the bottom electrode layer in the via.

Semiconductor random access memory and manufacturing method thereof

The present disclosure provides metal interconnect structures and fabrication methods thereof. An exemplary fabrication method of the metal interconnect structure includes providing a semiconductor substrate having a surface; forming a first metal layer on the surface of the semiconductor substrate; forming a dielectric layer on the first metal layer; forming contact through holes exposing a surface of the first metal layer, and trenches being over the contact through holes and connecting with the contact through holes in the dielectric layer; forming a first metal barrier layer on inner surfaces of the trenches and the contact through holes; forming a metal nitride barrier layer covering the first metal barrier layer on the inner surfaces of the trenches and the contact through holes; and forming a second metal layer to fill the trenches and the contact through holes.

Metal interconnect structure and fabrication method thereof

A method for fabricating a semiconductor structure includes providing a dielectric layer on a semiconductor substrate, forming an opening in the dielectric layer to expose a portion of the surface of the semiconductor substrate, forming a metal layer to fill up the opening, and removing the portion of the metal layer formed above the top surface of the dielectric layer by polishing. A metal oxide layer is formed on the surface of the metal layer after polishing. The method further includes removing the metal oxide layer from the top surface of the metal layer, forming a metal barrier layer on the top surface of the metal layer after the removal of the metal oxide layer to provide a more uniform thickness and a denser texture, and converting the metal barrier layer to a metal cap layer by introducing a silicon-containing gas onto a surface of the metal barrier layer.

Semiconductor structure and fabrication method thereof

A superjunction device in which corner portions of each annular-shaped second trench are composed of a plurality of alternately arranged first sides and second sides. The first sides are parallel to a plurality of parallel arranged first trenches in a current-flowing area, while the second sides are perpendicular to the first sides and the first trenches. Such design ensures that Miller indices of sidewalls and bottom face of any portion of each second trench belong to the same family of crystal planes. Moreover, with this design, the corner portions of the second trenches can be filled with a silicon epitaxial material at the same rate with the rest portions thereof, which ensures for the second trenches to be uniformly and completely filled without any defects in the corner portions and hence improve the performance of the superjunction device.

Superjunction device

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.

Semiconductor structures and fabrication methods including trench filling

The present invention discloses a method of manufacturing superjunction structure, which comprises: step 1, grow an N type epitaxial layer on a substrate having a (100) or (110) oriented surface; step 2, etch the N type epitaxial layer to form trenches therein; step 3, fill the trenches by P type epitaxial growth in the trenches by using a mixture of silicon source gas, halide gas, hydrogen gas, and doping gas. By using the manufacturing method according to the present invention, no void or only small voids are formed in the trenches after trench filling.

Growing community of inventors

Shanghai, China

Jiquan Liu