Mediatek Singapore Pte. Ltd.

Jiqing Cui

Huajiang Zhang

A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal.

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Singapore, Singapore

Jiqing Cui