National Semiconductor Corporation

Analog Devices,inc.

Analog Devices Global

Jipeng Li

Richard E Schreier

Matthew Louis Courcy

Hajime Shibata

Christian Ebner

Bernd Schafferer

Gabriele Manganaro

David Nelson Alldred

David Alldred

A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.

Charge pump supply with clock phase interpolation

In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Integrator output swing reduction

Embodiments of the present invention may include an apparatus and method to reduce an output swing in each stage of a multi-stage loop filter while also maintaining a desired signal transfer function for each respective stage. A given stage of the loop filter may include an integrator, a feedback path, a first cancellation path, and a second cancellation path. The first cancellation path may be coupled to the output of the integrator. The second cancellation path may be coupled to a feedback path provided about the input and output of the integrator. A first cancellation signal may be injected into the first cancellation path to reduce the output swing of the integrator. A second cancellation signal may be injected into the second cancellation path to minimize a change in the integrator's signal transfer function caused by the first cancellation signal.

Integrator output swing reduction technique for sigma-delta analog-to-digital converters

In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as 'trimming') of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-&#x3a3;&#x394;) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.

DAC circuit with pseudo-return-to-zero scheme and DAC calibration circuit and method

A data conversion stage circuit () for an opamp-shared pipeline analog-to-digital converter (ADC) () includes an over-range detection and recovery circuit including first and second switches (S, S) connected between respective input terminals () and output terminals () of the opamp () and both controlled by a first control signal, and a logic circuit () coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.

Pipeline ADC with memory effects achieving one cycle absolute over-range recovery

A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.

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Windham, NH, United States of America

Jipeng Li