Texas Instruments Corporation

Intersil Americas Inc.

Jinyu Yang

Steven Patrick Laur

Zbigniew Jan Lata

Dening Wang

Gregory George Romas, Jr

A circuit and method for switching between a system's internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the system using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing.

Advanced clock synchronization circuit

In a switch mode power supply, a circuit and method for switching between an internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the power supply using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing. In one embodiment, a power system comprises a plurality of power supplies connected in parallel to a common load and where each power supply is synchronized to the external clock when a stable external clock has been detected by each.

Advanced clock synchronization circuit for switch mode power supplies

Electrostatic discharge (ESD) protection circuits for self-protecting cascode stages are disclosed. In one example, an ESD protection circuit is described. A cascode stage is configured to selectively couple an output pad to a reference terminal. An ESD sensor may detect a change in voltage indicative of an ESD event occurring at the output pad, causing a gate drive to turn on the cascode stage to conduct ESD current in response to detection of the ESD event at the output pad. A leakage blocker is also included to prevent leakage current from the cascode stage to the gate drive while there is not an ESD event.

Electrostatic discharge trigger circuits for self-protecting cascode stages

A VCM power protection circuit that limits the maximum voltage that can occur across any of the VCM's output FETs, while at the same time providing some bias on a VCM output to direct a head toward a landing zone during power-up or any time there is a higher than normal voltage on the power supply.

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Plano, TX, United States of America

Jinyu Yang