Electronics and Telecommunications Research Institute

Jinyeong Kang

Chulsoon Park

Jinhee Lee

Jeonwook Yang

Sungjae Maeng

Dojin Kim

Youngkyu Choi

Kyuhwan Shim

Kyungho Lee

A manufacturing method of GaAs metal semiconductor FET is disclosed. The method comprises the steps of: preparing a GaAs substrate; depositing a silicon layer on the GaAs substrate; forming a first photoresist pattern on the silicon layer by means of well-known image reversal process; etching the silicon layer by means of photolithographic process using the first photoresist pattern as a mask to define ohmic contact regions of source/drain electrodes; forming a second photoresist pattern on the GaAs substrate after removal of the first photoresist pattern to define a channel region; injecting a predetermined quantity of silicon ions into the GaAs substrate to form the channel region; depositing a protective layer around the GaAs substrate after removal of the second photoresist pattern; annealing the substrate deposited with the protective layer to activate silicon ions of the remaining silicon layer and thus diffusing the activating silicon ions into the depth direction of the substrate; forming ohmic contacts on the substrate using an ohmic contact mask after removal of the protective layer and the remaining silicon layer; and forming a gate electrode by using a gate mask.

Manufacturing method of GaAs metal semiconductor FET

There is disclosed a manufacturing method of self-aligned GaAs FET using refractory gate with dual structure, the manufacturing method of the invention comprising the steps of: forming first photoresist pattern on a GaAs substrate to define an active region and ion-implanting n type impurity in the active region of the GaAs substrate; sequentially depositing a nitrogen-containing silicon layer and a metal layer on the substrate after removal of the first photoresist pattern; forming second photoresist pattern on the metal layer to define a gate; removing the silicon and metal layers using the second photoresist pattern as a gate mask to form the gate with dual structure of the silicon and metal layers; forming third photoresist pattern on the substrate to define source/drain regions after removal of the second photoresist pattern, and ion-implanting high-density impurity in the source/drain regions using the third photoresist pattern and the gate as a source/drain mask; annealing the substrate to make the silicon layer as upper side of the gate into metal-silicon-nitride material, and to make bottom portion of the metal layer as lower side of the gate into metal-silicon-nitride material; and forming ohmic contacts on the source/drain regions, respectively. A GaAs FET according to the invention is provided with a gate having low-resistance and improved schottky characteristics.

Manufacturing method of self-aligned GaAs FET using refractory gate of

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Daejeon, South Korea

Jinyeong Kang