Qualcomm Incorporated

Jinxia Bai

Thomas Sun

Chinnappa K Ganapathy

Amin Ansari

Rosario Cammarota

Jai N Subrahmanyam

Richard Senior

Vito Remo Bica

Durk L Van Veen

Michael Goldfarb

Fuyun Ling

Seong Taek Chung

Kevin Stuart Cousineau

Seokyong Oh

Michael Mao Wang

Murali Chari

A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware pre-processing of NDMA data in the read buffer and post-processing of NDMA data in the write buffer on blocks of a data stripe to process tensors in artificial neural networks.

Neural processing unit (NPU) direct memory access (NDMA) hardware pre-processing and post-processing

A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.

Neural processing unit (NPU) direct memory access (NDMA) memory bandwidth optimization

Aspects for generating compressed data streams with lookback pre-fetch instructions are disclosed. A data compression system is provided and configured to receive and compress an uncompressed data stream as part of a lookback-based compression scheme. The data compression system determines if a current data block was previously compressed. If so, the data compression system is configured to insert a lookback instruction corresponding to the current data block into the compressed data stream. Each lookback instruction includes a lookback buffer index that points to an entry in a lookback buffer where decompressed data corresponding to the data block will be stored during a separate decompression scheme. Once the data blocks have been compressed, the data compression system is configured to move a lookback buffer index of each lookback instruction in the compressed data stream into a lookback pre-fetch instruction located earlier than the corresponding lookback instruction in the compressed data stream.

Generating compressed data streams with lookback pre-fetch instructions for pre-fetching decompressed data from a lookback buffer

A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.

System, apparatus, and method for decompressing data

Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

IFFT processing in wireless communications

Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.

Methods and apparatus for dynamic packet reordering

Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.

Methods and apparatus for dynamic packet mapping

A system and method are provided for generating bit log likelihood ratio (LLR) values for two-layered Quadrature Phase-Shift Keying (QPSK) turbo decoding in a wireless communications user terminal (UT). The method includes receiving a two-layered QPSK signal with an energy ratio that is unknown, but typically defined as either kor k. The method selects a mismatched energy ratio (k) between kand k, and generating bit LLR values for two-layered QPSK turbo decoding, using the mismatched kenergy ratio. For example, if the received two-layered QPSK signal is known to have an energy ratio of about 4 or about 6.25. Then, kis selected to be about 5.0625. Alternately stated, the mismatched kenergy ratio in selected by determining the approximate midpoint between kand k.

Bit log likelihood ratio evaluation

Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.

Parallel bit interleaver for a wireless system

A multimedia distribution system is disclosed. The distribution system includes a transmitter unit that distributes content from a content provider to one or more wireless subscriber units. The transmitter unit includes a decoder configured to determine whether a plurality of incoming packets include one or more erasures, a transmitter configured to transmit the packets to a receiving unit, and an error detection code generator configured to generate an error detection code for each of the packets transmitted to the receiver unit, the error detection code being modified for each of the erased packets so that the receiver unit will be able to identify the erased packets.

Forward error correction in a distribution system

Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.

Growing community of inventors

San Diego, CA, United States of America

Jinxia Bai