Rebellions Inc.

Jinwook Oh

Jinseok Kim

Wongyu Shin

Sungyeob Yoo

Hyunsung Kim

Kyeongryeol Bong

Karim Charfi

Hongyun Kim

Juyeong Yoon

Miock Chi

Donghan Kim

Chang-Hyo Yu

Sunghyun Park

Jaewan Bae

Yoonho Boo

Hyunho Kim

A method for processing tasks in parallel is performed by at least one processor, and includes performing a first task associated with a first instruction, determining whether the first instruction is a burst load instruction, in response to determining that the first instruction is the burst load instruction, acquiring a second instruction, and performing a second task associated with the acquired second instruction, in which the first task and the second task are performed in parallel.

Parallel overlapping burst load operations

The present disclosure relates to a data processing device. The data processing device includes: a storage module configured to store a plurality of entries included in a first matrix and position information associated with each of the plurality of entries; a data load module configured to receive the plurality of entries and position information from the storage module, generate a determination result as to whether each of the received entries is zero, and generate an instruction sequence based on the determination result and the position information; and a processing unit configured to generate an operation result by using some of the plurality of entries in accordance with the instruction sequence.

Device and method for operation of data

A neural processing device and a method for managing tasks thereof are provided. The neural processing device includes a neural core configured to perform a task and generate a completion signal for completion of the task, a core global configured to transfer task information for the task to the neural core and receive the completion signal of the task from the neural core, and a task manager configured to generate and transmit the task information to the core global, receive the completion signal from the core global, generate a completion report, and transmit the completion report.

Processing device and method for managing tasks thereof

A neural processing device is provided. The neural processing device comprises a plurality of neural processors, a shared memory shared by the plurality of neural processors, a plurality of semaphore memories, and global interconnection. The plurality of neural processors generates a plurality of L3 sync targets, respectively. Each semaphore memory is associated with a respective one of the plurality of neural processors, and the plurality of semaphore memories receive and store the plurality of L3 sync targets, respectively. Synchronization of the plurality of neural processors is performed according to the plurality of L3 sync targets. The global interconnection connects the plurality of neural processors with the shared memory, and comprises an L3 sync channel through which an L3 synchronization signal corresponding to at least one L3 sync target is transmitted.

Neural processing device and method for synchronization thereof

A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.

Neural core, neural processing device including same, and method for loading data of neural processing device

A neural processing device is provided. The neural processing device includes a plurality of processing engine groups, a first memory shared by the plurality of engine groups, a first interconnection configured to transmit data between the first memory and the plurality of processing engine groups. The neural processing device is configured to provide hardware resource to the plurality of processing engine groups. At least one of the plurality of processing engine groups includes a plurality of processing engines, each of the plurality of processing engines includes an array of a plurality of processing elements interconnected by a mesh style network, the processing elements being reconfigurable. The neural processing device includes a second memory shared by the plurality of processing engines, and a second interconnection configured to transmit data between the second memory and the plurality of processing engines.

Neural processing device

A reconfigurable on-chip memory bank, reconfigurable on-chip memory, system-on-chip having same mounted thereon, and method for using reconfigurable on-chip memory is provided. The reconfigurable on-chip memory bank comprises a cell array in which a plurality of cells are arranged and data are stored, a first path unit configured to move data in the cell array, a second path unit configured to move data in the cell array and a bank controller operably coupled with the first and second path units, and configured to determine, according to a path control signal during runtime, data path which data are to be transmitted to or received from, to use a first address system when the first path unit is determined to be the data path, and to use a second address system different from the first address system when the second path unit is determined to be the data path.

Reconfigurable on-chip memory bank, reconfigurable on-chip memory, system-on-chip having same mounted thereon, and method for using reconfigurable on-chip memory

The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.

Processing element, neural processing device including same, and multiplication operation method using same

The disclosure relates to an apparatus for high frequency trading. The apparatus includes one or more memories, at least one reconfigurable processor coupled to the one or more memories, and a dedicated accelerator preconfigured for the machine learning model. The one or more processors receive market-related information from one or more market-related information servers and generates market prediction reference data based on the market-related information. The dedicated accelerator performs operations for the machine learning model with the market prediction reference data to generate future market prediction data. The at least one reconfigurable processor generates an order signal based on the future market prediction data and transmits the order signal to a target exchange server.

Apparatus for high frequency trading and method of operating thereof

A neural processing device, a processing element included therein and a method for operating various formats of the neural processing device are provided. The neural processing device includes at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises at least one processing element, each of the at least one processing element receives an input in a first format and thereby performs an operation, and receives an input in a second format that is different from the first format and thereby performs an operation if a format conversion signal is received, and the first format and the second format have a same number of bits.

Neural processing device, processing element included therein and method for operating various formats of neural processing device

A neural processing device and a method for converting data thereof are provided. The neural processing device comprises a first compute unit configured to receive first input data in first precision and generate first output data in the first precision by performing calculations, a second compute unit configured to receive second input data in second precision which is different from the first precision and generate second output data in the second precision by performing calculation, and a first converting buffer configured to receive and store the first output data, generate the second input data by converting the first output data into the second precision, and transmit the second input data to the second compute unit.

Neural processing device and method for converting data thereof

A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.

A method for high frequency trading is provided, which is performed by one or more processors, and includes calculating a latency for a market order for each of a plurality of candidate batch sizes, selecting a batch size from among the plurality of candidate batch sizes based on the calculated latency, generating input data corresponding to the selected batch size using market data for a target item, using a machine learning model, generating prediction data for the target item at a future time point associated with the selected batch size, based on the generated input data, and generating order data for the target item based on the generated prediction data.

Method and system for high frequency trading

A method for adjusting a hardware performance for high frequency trading is provided, which is performed by one or more processors, and includes receiving context information including at least one of a traffic of market data for one or more target items or a computational complexity of using a machine learning model performed based on the market data, determining whether or not to change a processing performance of the hardware based on the received context information, and changing a resource supplied to the hardware based on the determination result for changing the processing performance.

Growing community of inventors

Seongnam-si, South Korea

Jinwook Oh