Samsung Electronics Co., Ltd.

International Business Machines Corporation

Korea Advanced Institute of Science and Technology

Jinwook Jung

Wontaek Seo

Insu Jeon

Youngtek Oh

Gi-Joon Nam

Gustavo Enrique Tellez

Lakshmi Narasimha Reddy

Seunggeol Nam

Jae-Woo Seo

Hyeokshin Kwon

Youngsoo Shin

Sanghun Kim

Roman Vaculin

Richard Harold Boivie

Paul Gerard Villarrubia

Christopher J Berry

Michael H Wood

Shyam Ramji

Junghwan Kim

James Thomas Rayfield

Robert Alan Philhower

Enriquillo Valdez

Venkata Sitaramagiridharganesh Ganapavarapu

Frank Musante

Cindy ShuiKing Washburn

Jiyoung Choi

Yuna Choi

Tae-hyun Han

Youngduk Suh

Dongkyeng Han

Ohkug Kwon

Sangbeom Park

Kukbin Choi

Changlae Lee

Keyjo Hong

A semiconductor fabrication apparatus comprising a light source configured to emit light, a substrate stage arranged to receive a substrate exposed to the emitted light, a reticle arranged between the substrate stage and the light source, and a reticle stage arranged to receive the reticle. The reticle stage including a lower plate, an upper plate arranged above the lower plate, an actuator connected to the lower plate configured to move in a direction parallel to the upper plate, a first cable slab arranged between the upper plate and the lower plate and connected to one side of the actuator, and a first cable cover that surrounds an outer periphery of the first cable slab and contacts the lower plate when the first cable slab becomes bent.

Semiconductor fabrication apparatus

Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

Transistor including electride electrode

A tomographic image processing apparatus including a display, an input interface configured to receive an external input, a storage storing an input tomographic image of an object, and at least one processor configured to control the display to display the input tomographic image, determine a material combination to be separated from the input tomographic image, and control the display to display material separation information corresponding to the determined material combination for a region of interest selected in the input tomographic image based on the external input. The input tomographic image is a spectral tomographic image having a plurality of tomographic images respectively corresponding to a plurality of energy levels.

Tomographic image processing apparatus and method of separating material of object in spectral tomographic image, and computer program product

A method verifies an authenticity, integrity, and provenance of outputs from steps in a process flow. One or more processor(s) validate one or more inputs to each step in a process flow by verifying at least one of a hash and a digital signature of each of the one or more inputs. The processor(s) then generate digital signatures that cover outputs of each step and the one or more inputs to each step, such that the digital signatures result in a chain of digital signatures that are used to verify an authenticity, an integrity and a provenance of outputs of the one or more steps in the process flow.

Electronically verifying a process flow

A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

Silicene electronic device

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Multi-cycle latch tree synthesis

A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

Semiconductor device

A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

Critical path straightening system based on free-space aware and timing driven incremental placement

Growing community of inventors

Daejeon, South Korea

Jinwook Jung