Samsung Electronics Co., Ltd.

Jinwoo Bae

Sunghee Han

Sangho Lee

Yoosang Hwang

Yoonyoung Choi

Boun Yoon

Junwon Lee

Jonghyuk Park

Junghwan Oh

Jaehwan Cho

Seungjin Kim

Sejin Park

Wooyoung Choi

Yanghee Lee

Ilyoung Yoon

Byunghyun Lee

Hyesung Park

Byeongjoo Ku

Sangjae Park

Deoksung Hwang

Hangeol Lee

Sungsoo Yim

Hyunjoo Choi

Bowo Choi

Hyunsil Hong

Myungjae Jang

Byeongmoo Kang

Seongmo Koo

Woonghwi Bae

Chaelin Yoon

Sunwoo Heo

Youngho Koh

A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.

Semiconductor device

The disclosure relates to a 5Generation (5G) or pre-5G communication system for supporting a higher data rate than a 4Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a base station in a wireless communication system is provided. The apparatus includes: a master Field Programmable Gate Array (FPGA); a plurality of slave FPGAs controlled by the master FPGA; and an address masker coupled to the master FPGA and the plurality of slave FPGAs, wherein the address masker is configured to: receive different address bits assigned respectively to the plurality of slave FPGAs by the master FPGA; for the different address bits, mask bit values at a specific position with the same value; and transmit masked address bits corresponding respectively to the plurality of slave FPGAs.

Apparatus and method for operating multiple FPGAS in wireless communication system

A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device

A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.

Semiconductor device including insulating patterns and method for forming the same

Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

Methods of fabricating capacitor and semiconductor device and semiconductor devices and apparatus including the same

A semiconductor device includes a transistor on a semiconductor substrate including a first area and a second area, and having a gate structure and an impurity area, a first interlayer insulating film covering the transistor, and having a contact plug electrically connected to the impurity area, a capacitor including a lower electrode on the first interlayer insulating film in the second area and electrically connected to the contact plug, a dielectric film coating a surface of the lower electrode, and an upper electrode on the dielectric film, and a support layer in contact with an upper side surface of the lower electrode to support the lower electrode, and extending to the first area, in which the support layer has a step between the first area and the second area.

Methods of forming a capacitor, semiconductor device, and fine pattern, and semiconductor device formed by the methods

A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

Semiconductor device and a fabrication method thereof

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Yongin-si, South Korea

Jinwoo Bae