Samsung Electronics Co., Ltd.

Jintae Noh

Kihyun Hwang

Sunggil Kim

Ji-Hoon Choi

Seulye Kim

Byoungsun Ju

Jung-Hwan Lee

Woonkyung Lee

Bonyoung Koo

Jin-Kyu Kang

Jeeyong Kim

Dongkyum Kim

Jung Ho Kim

Jaeyoung Ahn

Hanvit Yang

Sanghoon Lee

Jung-Hwan Kim

Eun-Young Lee

Sangsoo Lee

Phil Ouk Nam

Siyoung Choi

Bio Kim

Dongchul Yoo

SeungHyun Lim

Hyun-Jin Shin

Hong Suk Kim

HongSuk Kim

Sung Gil Kim

Su-Jin Shin

A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

Three dimensional semiconductor memory with residual memory layer

A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.

Semiconductor device and method for fabricating the same

A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

Semiconductor memory devices

A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.

Three-dimensional semiconductor device

The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.

Method of manufacturing a three-dimensional semiconductor memory device

Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.

Semiconductor device and method of fabricating the same

Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Semiconductor devices

Semiconductor devices and methods of manufacturing the same

Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

Nonvolatile memory devices

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Yongin-si, South Korea

Jintae Noh