Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Samsung Electro-mechanics Co., Ltd.

Lg Innotek Co., Ltd.

Kookmin University

Jinsoo Park

Dongwoo Lee

Kangha Lee

Yoona Park

Sungwoo Sul

Junyoung Lim

Myung Jun Park

Hyunpyo Lee

Dae Kyung Ahn

Sangil Park

Baek Ki Kim

Junwon Bae

Jaeyoon Lee

Seungdo Han

Dongcheol Lee

Jungbum Kim

Seunghee Ryu

Beom Seok Shin

Kilhyung Cha

Serhoon Lee

Jiseong Park

Wookyung Sung

Junggi Lee

Sungjin Huh

SoEun Choi

Jinha Choi

Gilwon Hong

Jong Ho Lee

Jaeho Kim

Jung Min Kim

Ji Hye Han

Kwangwook Chun

Yunho Kim

Yeon Song Kang

Hyeokjin Song

Hosang Yoon

Junbo Yun

Byoungkon Park

Jaeseok Oh

Seungpyo Han

Eunme Park

BeomSuk Kang

Eun-Jin Kim

Byungjun Jang

Daesung Kang

Hyungoo Yoon

Hoseok Choi

Gihoon Lee

Mansung Kim

A multilayer electronic component includes a body including first and second surfaces opposing each other in the first direction, and third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, a first external electrode including a first base electrode layer including glass and Ni and disposed on the third surface, a first intermediate electrode layer including an alloy containing Sn and Ni and disposed on the first base electrode layer, and a first conductive resin layer including a resin and a metal and disposed on the first intermediate electrode layer and extending to the first and second surfaces, a second external electrode including a second base electrode layer disposed on the fourth surface, a second intermediate electrode layer disposed on the second base electrode layer, and a second conductive resin layer disposed on the second intermediate electrode layer.

Multilayer electronic component and method of manufacturing the same

A multilayer capacitor includes a capacitor body including an active region having a dielectric layer, and first and second internal electrodes, and an upper cover region and a lower cover region respectively disposed above and below the active region, and including first to sixth surfaces; and first and second external electrodes disposed on both end portions of the capacitor body in the second direction, respectively, and connected to the first and second internal electrodes, respectively. The first and second external electrodes include first and second conductive layers disposed on the third and fourth surfaces, respectively; first and second conductive resin layers disposed on the first and second conductive layers, respectively; and first and second plating layers disposed on the first and second conductive resin layers, respectively, and contacting the first and second conductive layers in the upper or lower cover region, respectively.

Multilayer capacitor

An electronic component includes: a body including a dielectric layer and internal electrodes, and including first to sixth surfaces; a first external electrode including a connection portion on the third surface, and first and third band portions respectively on the first and second surfaces; a second external electrode including a connection portion on the fourth surface, and second and fourth band portions respectively on the first and second surfaces; an insulating layer disposed on the connection portions, and covering the second surface and the third and fourth band portions; plating layers respectively disposed on the first and second band portions; and first and second additional electrode layers respectively disposed between the connection portion and the third surface and between the connection portion and the fourth surface. The first or second external electrode includes copper. The first or second additional electrode layer includes one of nickel and an alloy of nickel.

Multilayer electronic component

A multilayer electronic component includes a body and first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction; a first external electrode including a first connection portion disposed on the third surface, and a first band portion extending from the first connection portion to a portion of the first surface; a second external electrode including a second connection portion disposed on the fourth surface, and a second band portion extending from the second connection portion to a portion of the first surface; an insulating layer disposed on the second surface and extending to the first and second connection portions; a first plating layer disposed on the first band portion; and a second plating layer disposed on the second band portion, wherein the insulating layer includes an oxide including silicon (Si).

Mutilayer electronic component

An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

Line interleaving controller, image signal processor and application processor including the same

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The disclosure is A first apparatus for estimating a delay time in a synchronization system is provided. The first apparatus includes a detector configured to detect a request signal generated by a second apparatus, and a generator configured to generate a response signal corresponding to the request signal and output the response signal. The request signal is received through a cable from the second apparatus and the response signal is transmitted to the second apparatus through the cable.

Apparatus in synchronization system and methods for operating the same

A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

System-on-chip for AT-SPEED test of logic circuit and operating method thereof

The present invention relates to a communication technique for convergence of IoT technology and a 5G communication system for supporting a higher data transfer rate beyond a 4G system, and a system therefor. Also, the present invention provides a method for determining a location of a base station, the method comprising the steps of: receiving, from a terminal, a first message including location information of the terminal; and determining location information of the base station on the basis of the received location information of the terminal.

Method and apparatus for determining location of base station in mobile communication system

System-on-chip for at-speed test of logic circuit and operating method thereof

An approach is provided for configuring multiple interferers. An interference effect minimum protective distance is calculated in response to detection of an input of an interferer parameter. Physical (PHY) layer modeling is performed to individually apply a pathloss caused by a separation distance between an interferer node and a victim and apply a pathloss of each node to an attenuator and a transmitter amplifier in an HW manner. MAC layer modeling is performed to determine a transmission node and a transmission time using Markov chain or determine a transmission node and a transmission time using a result log file of an external MAC simulator and a transmission/reception time is reflected in an HW manner by turning ON/OFF a switch. Multiple correlated interferer signals are generated for analyzing an effect of frequency interference in view of both of PHY and MAC layers.

Device and method for configuring multiple interferers

Remote controller

TV receiver

Growing community of inventors

Seoul, South Korea

Jinsoo Park