Samsung Electronics Co., Ltd.

Jinsoo Bae

Sangwoo Pae

Hyunggyun Noh

Deok-Seon Choi

Il-Joo Choi

Gun-Hee Bae

Keunho Rhew

Iljoo Choi

Deokseon Choi

A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Semiconductor package including stacked chip structure

A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

Semiconductor package device

Growing community of inventors

Seongnam-si, South Korea

Jinsoo Bae