Agere Systems Inc.

Syntest Technologies, Inc.

Jinsong Liu

Laung-Terng Wang

Shianling Wu

HaiFeng Zhou

Zhigang Jiang

Hao-Jan Chao

Wen Zhu

Fangfang Li

Jianping Yan

Feifei Zhao

Lizhen Yu

Qiangao Xu

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Multiple-capture DFT system to reduce peak capture power during self-test or scan test

A method of transitioning a port in a communication system from an active state to a standby state includes the steps of transmitting a signal to transition the port to the standby state, and, upon transmission of the signal to transition the port to the standby state, transitioning the port from the active state into the standby state without entering a suspended state. The port may be a physical layer interface port and the communication system may be an IEEE 1394-compliant communication system.

Transitioning of a port in a communications system from an active state to a standby state

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Shanghai, China

Jinsong Liu