Samsung Electronics Co., Ltd.

Jinseong Yun

Kyudong Lee

Jaejun Lee

Sungjoo Park

Young-ho Lee

Taeyoung Oh

Seungjin Lee

Young Nam Yun

Jonghoon Kim

Jong-Geon Lee

Hyongryol Hwang

Taekwoon Kim

Ki-Heung Kim

Jeonghyeon Cho

Kyoungsun Kim

Heejin Cho

Yoo-Jeong Kwon

Yoonjae Jeong

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

Memory module for performing one-time programmable (OTP) addressing operation to store unique ID of each memory device in an ID storge region of each memory device, and storage device including the same

A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.

Memory module and memory system having the same

An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

Electronic device having multilayered substrate and manufacturing method thereof

A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.

Power management integrated circuit for monitoring output voltage, memory module including power management integrated circuit and memory device, and operating method of memory module

Power management integrated circuit (PMIC), memory module and computing system including a PMIC, and method of operating a memory system

A semiconductor memory module includes a memory printed circuit board (PCB) that includes first connectors, a second connector, and a third connector configured to be connectable with an external device, memory devices that are mounted on the memory PCB and are connected with the first connectors, and a power management integrated circuit that is mounted on the memory PCB, receives a first voltage through the second connector, generates a second voltage from the first voltage, and supplies the second voltage to the memory devices. The power management integrated circuit adjusts the second voltage depending on a difference between a signal received through the third connector and the second voltage.

Semiconductor memory modules including power management integrated circuits

A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.

Power management integrated circuits and semiconductor memory modules including power management integrated circuits

Growing community of inventors

Suwon-si, South Korea

Jinseong Yun