Advanced Micro Devices Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Jinqlih Sang

Bahadir Erimli

Ian S Crayford

Thomas J Runaldue

David Chen

Denise Kerstein

Jayant Kadambi

Philip Simmons

Edward Yang

Rahul Durve

Kandasamy Aravinthan

Manoj Lakshmy Gopalakrishnan

Shashank C Merchant

Peter Ka-Fai Chow

Eric Tsin-Ho Leung

Michael VengChong Lau

A network device, such as a network switch, can include an ingress to receive data packets from a network. The ingress can communicate with an egress included in the network device though a fabric included in the network device. At least one of ingress and the egress can enqueue a data packet prior to receipt of all cells of the data packet. The ingress can also commence with dequeue of the cells of the received data packet prior to receipt of the entire data packet from the network. At least one of ingress and the egress can process the data packets using cut-through processing and store-and-forward processing. In a case of cut-through processing of a data packet at both the ingress and the egress of a network device, such as CIOQ switch, the fabric can be allocated to provide a prioritized virtual channel through the fabric for the data packet.

Early queueing network device

Multiple network switch modules have memory interfaces configured for transferring packet data to respective buffer memories. The memory interfaces are also configured for transfer among each other data units of data frames received from different network switch modules. A shared switching logic monitors (&ldquo;snoops&rdquo;) the data units as they are transferred between network switch modules, providing a centralized switching decision logic for multiple network switch modules. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads. A preferred embodiment includes a distributed memory interface in between the network switch modules and a shared memory system.

Apparatus and method for monitoring data frames by a shared switching logic during simultaneous accessing of multiple network switch buffers

Multiple network switch modules have memory interfaces configured for transferring packet data to respective buffer memories. The memory interfaces are also configured for transfer among each other data units of data frames received from different network switch modules. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads. An alternative embodiment includes a distributed memory interface in between the network switch modules and a shared memory system, where the width of the data bus of the shared width memory system equals the total number of bits on the data buses of the switch modules.

Apparatus and method for simultaneously accessing multiple network switch buffers for storage of data units of data frames

A network switch configured for switching data packets across multiple ports uses an external memory to store data frames. When a data frame is transmitted to the external memory, a frame header portion of the data frame is stored on the switch for processing by decision making logic. The switch memory is configured to store a number of the frame headers corresponding to each port on the switch along with frame pointer information indicating the location in the external memory where the data frame is stored.

Decision making engine receiving and storing a portion of a data frame in order to perform a frame forwarding decision

A network switch configured for switching data frames across multiple ports utilizes an efficient arbiter to store the data frames. Each port possesses queuing logic for requesting a free pointer from a free buffer queue. A multi-level arbitration logic arbitrates all the requests of equal priority from the network switch ports in a round robin scheme. The arbitration logic comprises a plurality of cells that cascaded to output an acknowledgement signal in response to an inhibit signal and a request signal as well as a counter that is incremented upon an asserted acknowledgement signal.

Weighted round robin cell architecture

A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure.

Split-queue architecture with a first queue area and a second queue area and queue overflow area having a trickle mode and an overflow mode based on prescribed threshold values

A network switch having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on a selected network port. The network switch includes a queue for storing free frame pointers, each specifying available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated on a half-duplex network port by transmitting a phantom packet to a transmitting network station if the output buffer of a destination port exceeds a programmed high threshold, or if the output buffer of the destination port exceeds a low programmed threshold and the queue of free frame pointers falls below a low programmable threshold. The switch thus provides flexibility in providing selective collisions with transmitting stations to minimize the possibility of network congestion without wasting network bandwidth with unnecessary collisions.

Method and apparatus providing programmable thresholds for half-duplex flow control in a network switch

A network having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on full-duplex network ports. The network switch includes a queue for storing free frame pointers that specify available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated based on the number of available frame pointers by transmitting a PAUSE frame having a selected PAUSE interval to a transmitting network station. Specifically, a full-duplex port will output a PAUSE frame having a short, medium, or long programmed pause interval if the free buffer pool of available frame pointers falls below a high, medium, or low programmable threshold, respectively. The switch thus provides flexibility in generating variable-length PAUSE control frames to minimize wasting network bandwidth.

Growing community of inventors

Fremont, CA, United States of America

Jinqlih Sang