Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries U.S. Inc.

Jinping Liu

Jiehui Shu

Hui Zang

Haigou Huang

Bharat V Krishnan

Min Dai

Haifeng Sheng

Haiting Wang

Huang Liu

Liang Choo Hsia

Tao Han

Michael Patrick Chudzik

Hong Yu

Huy Cao

Mei Sheng Zhou

Shesh Mani Pandey

Yanxiang Liu

Joseph Francis Shepard, Jr

Xiaodong Yang

Bongki Lee

Min-Hwa Chi

Laertis Economikos

Shahab Siddiqui

Garo Jacques Derderian

Zhenyu Hu

Daniel J Jaeger

Scott Beasor

Chung Foong Tan

Jianwei Peng

David Paul Brunco

Xintuo Dai

Jinsheng Gao

Tek Po Rinus Lee

Alex K H See

Wei Zhao

Chih-Chiang Chang

Pei Liu

Ruilong Xie

John H Zhang

Paul Raymond Besser

Hoon Sik Kim

Kisik Choi

Guillaume Bouche

Olov B Karlsson

Jody Alan Fronheiser

Yiheng Xu

Yanfeng Wang

Hai Cong

Hsien-Ching Lo

Amol Ramesh Joshi

Kheng Chok Tee

Zhiguo Sun

Shiang Yang Ong

Man Gu

Dong Kyun Sohn

Ashish Bodke

Zhendong Hong

Moosung M Chae

Maryjane Brodsky

Xiaoqiang Zhang

Seung Yeon Kim

Qiang Fang

Chang Seo Park

Vara Govindeswara Reddy Vakada

Shishir K Ray

Hui Zhan

Usha Raghuram

Bangun Indajang

Takashi Ando

Andy C Wei

Elgin Kiok Quek

Terry Allen Spooner

Siddarth A Krishnan

Xusheng Kevin Wu

Alex See

Murat Kerem Akarvardar

Nicholas V Licausi

Jae Gon Lee

Keith Howard Tabakman

Timothy James McArdle

Xiang Hu

Ravi Prakash Srivastava

Michael Vincent Aquilino

Rui Chen

Shariq Siddiqui

Balaji Kannan

Zhao Lun

Paul Andrew Ronsheim

Baofu Zhu

Matthew W Stoker

Charlotte DeWan Adams

Donghun Kang

Songkram Srivathanakul

Patrick D Carpenter

Meisheng Zhou

Ganesh S Samudra

Chang Ho Maeng

Junsic Hong

Yue Zhong

Byoung Youp Kim

One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

IC product comprising an insulating gate separation structure positioned between end surfaces of adjacent gate structures

A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

Transistor comprising an air gap positioned adjacent a gate electrode

Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

Electrical fuse formation during a multiple patterning process

A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.

FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin

Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

Multi-step insulator formation in trenches to avoid seams in insulators

A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3&#xd7; fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3&#xd7; fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

Device with large EPI in FinFETs and method of manufacturing

The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

Method of forming semiconductor material in trenches having different widths, and related structures

At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the silicon germanium of the second portion that is below the gate structure.

Method, apparatus and system for improved performance using tall fins in finFET devices

In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Methods of multiple patterning. First and second mandrel lines are formed on a patternable layer. Sidewall spacers are formed on the patternable layer adjacent to the first mandrel line and adjacent to the second mandrel line. A portion of the first mandrel line is removed to form a gap in the first mandrel line. A gapfill material is deposited in the gap in the first mandrel line. The gapfill material and sidewall spacers are composed of the same material.

Multiple patterning with variable space mandrel cuts

The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

Capping structure

A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

Method for forming replacement air gap

A method includes forming a first hard mask layer above a substrate. The first hard mask layer is patterned to define a plurality of fin openings and at least a first diffusion break opening. A first etch process is performed to define a plurality of fins in the substrate and a first diffusion break recess in a selected fin. A first dielectric layer is formed between the fins and in the first diffusion break recess to define a first diffusion break. A second hard mask layer having a second opening positioned above the first diffusion break is formed above the first hard mask layer and the first dielectric layer. A second dielectric layer is formed in the second opening. The second hard mask layer is removed. A second etch process is performed to recess the first dielectric layer to expose upper portions of the plurality of fins.

Method for forming single diffusion breaks between finFET devices and the resulting devices

One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

Methods of forming replacement gate structures on transistor devices

Growing community of inventors

Ballston Lake, NY, United States of America

Jinping Liu