International Business Machines Corporation

Varian Semiconductor Equipment Associates, Inc.

Jinning Liu

Kangguo Cheng

Ruilong Xie

Tenko Yamashita

Chanro Park

Julien Frougier

Robert C Wong

Dongbing Shao

Cheng Chi

Julian G Blake

Richard S Muka

Steven Raymond Walther

Jonathan Gerald England

Jingyu Lian

Kyu-Ha Shim

Jing Sha

Scott C Holden

Reuel B Liebert

Sandeep Mehta

Ukyo Jeong

Shruthi Venkateshan

A semiconductor structure comprises a substrate defining a first axis and a second axis orthogonal to the first axis, a first nanosheet region disposed on the substrate and defining a first channel width along the second axis, a first gate disposed around the first nanosheet region, a second nanosheet region disposed on the substrate and defining a second channel width along the second axis less than the first channel width of the first nanosheet region and a second gate disposed around the second nanosheet region.

Nanosheet transistor devices with different active channel widths

Ground rule verification ('GRV') design layouts may be automatically generated based on one or more design macros. The GRV design layout may be tested based on the one or more design macros by violating one or more ground rules using one or more GRV ranges. The testing may include electrical testing of the one or more GRV design layouts based on the one or more design macros. The one or more ground rules may be automatically selected and approved the based upon a degree of violation acceptability.

Automatic generation of ground rule verification macros

A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.

Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield

Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.

Techniques for temperature controlled ion implantation

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Andover, MA, United States of America

Jinning Liu