Samsung Electronics Co., Ltd.

Jinnam Kim

Jungah Choi

Kwangjin Moon

Hoonjoo Na

Hakseung Lee

Sung-Kyung Lee

Chris Bangle

Hyoukyung Cho

Seokho Kim

Taeseong Kim

Sujin Oh

Kang-Doo Kim

Sungjae Lee

Dongwon Chun

Jaewon Choi

Myunggyu Kim

Jinsook Park

Dohyung Ha

Junghoon Hwang

Kyoungmin Lee

Dae Kyun Lee

Seungbin Im

Youngsun Shin

Hyungjun Jeon

Sang Hoon Yoon

Kyoungsoo Sun

Hoyoung Joo

Eunsuk Jung

Ilmo Ahn

Hayong Jang

Sangjun Park

JoonHo Lee

Dong Won Chun

Hojin Lee

Dong-Chan Lim

Rakhwan Kim

Eunji Kim

Jiyeun Yoon

Ho-Jin Lee

Hayoung Jang

Kichul Park

Kunsang Park

Myungjoo Park

Jaewon Hwang

Pilkyu Kang

KyoungWoo Lee

Nami Mo

Anthony Dongick Lee

Daesuk Lee

Sujung Youn

Juyoung Jung

Sangcheol Na

Yoonsuk Kim

Eunji Jung

Doohwan Park

A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

Semiconductor device including via structure

A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite from each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via extending from the second surface of the first semiconductor substrate and into at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

Semiconductor devices having penetration vias

A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

Semiconductor packages

A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

Semiconductor packages and methods of manufacturing the semiconductor packages

Washing machine

A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

Washing machine with clothes dryer

Semiconductor packages stacked by wafer bonding process and methods of manufacturing the semiconductor packages

A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

Apparatus for etching substrate bevel and semiconductor fabrication method using the same

A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

Semiconductor device

A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

Semiconductor devices having penetration vias with portions having decreasing widths

Growing community of inventors

Seoul, South Korea

Jinnam Kim