Taiwan Semiconductor Manufacturing Comp. Ltd.

Jinn-Yeh Chien

Shu-Chun Yang

Chewn-Pu Jou

Robert Bogdan Staszewski

Yung-Chow Peng

Jaw-Juinn Horng

Chih-Hsien Chang

Feng Wei Kuo

Chung-Chieh Yang

Szu-Lin Liu

Mao-Hsuan Chou

Kuang-Kai Yen

Kuan-Yu Lin

Chen-Ting Ko

Hao-Jie Zhan

Sheu Shey Ping

An integrated circuit includes a first circuit having a loopback path electrically coupled to an inverter and a test circuit having a controller and a counter. The test circuit is electrically coupled to the first circuit, and the controller is configured to select the loopback path. The first circuit is configured to receive a first voltage signal and to generate an oscillating signal from the received first voltage signal. The first voltage signal is either a substantially low logic level signal or a substantially high logic level signal. The counter is configured to count oscillations of the oscillating signal.

Integrated circuit and method of testing

An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.

Some embodiments of the present disclosure provide a method including turning on a noise-measuring system for a device under test (DUT) with the DUT turned off; measuring a first phase noise caused by the noise-measuring system; turning on the DUT; measuring a second phase noise caused by the noise-measuring system and the DUT; and subtracting the first phase noise from the second phase noise to obtain a third phase noise caused by the DUT.

Device testing and monitoring method thereof

An integrated circuit includes a first circuit and a test circuit. The test circuit is configured to test the timing of a first circuit. The first circuit includes a plurality of flip-flops and a plurality of data paths. Each data path of the plurality of data paths is connected to one or more of the plurality of flip-flops. The test circuit includes a plurality of loopback paths, a controller, a multiplexer connected to the plurality of loopback paths and a counter connected to the multiplexer. The controller is configured to select a path from the plurality of loopback paths and the plurality of data paths. The multiplexer is configured to selectively output a first signal including an oscillation frequency. The first signal is applied to the selected path and the counter is configured to measure the oscillation frequency of the first signal.

A calibration procedure that uses direct measurement of digital phase error performance for low cost calibration of all-digital phase locked loop (ADPLL)/digitally-controlled oscillator (DCO) is described. Direct measurement of digital phase error, or difference in digital phase error, is used to adjust the operating point of the DCO and thereby determine the operating point that provides the optimal phase noise of the output signal. Calibration may be performed at any time so that changes in external factors such as process, voltage and temperature (PVT) may be incorporated into the setting of the operating point of the DCO.

DCO phase noise with PVT-insensitive calibration circuit in ADPLL applications

A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

In situ on the fly on-chip variation measurement

A device includes a delay line, a first readout circuit electrically connected to the delay line, a second readout circuit electrically connected to the delay line, and a phase interpolator electrically connected to the second readout circuit.

Time-to-digital converter and related method

An embodiment is a device including a control circuit, a time-to-digital converter circuit coupled having a first output coupled to a first input of the control circuit, and a gating circuit having a first input coupled to a first signal, a second input coupled to a second signal, and an output coupled to a first input of the time-to-digital converter circuit, an output of the control circuit coupled to a second input of the time-to-digital converter circuit and to a third input of the gating circuit.

System and method for a time-to-digital converter

Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply.

Power supply regulator

This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.

Smart edge detector

An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Built in self test for transceiver

System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.

Built-in bit error rate test circuit

This invention discloses a phase interpolation controller for a clock and data recovery circuit receiving an indication of a phase relationship between a first and a second signal, the phase interpolation controller comprises a plurality of serially coupled bi-directional shift-registers, wherein when the received indication indicates the first signal is ahead of the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in one of the bi-directions, and when the received indication indicates the first signal is behind the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in the other of the bi-directions.

Digital phase interpolation control for clock and data recovery circuit

In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D) to trigger a first flip-flop having a first clock in a transmitter domain (e.g., clock CLK_D) as input data for the first flip-flop. The clock CLK_Dthrough a delay cell also triggers a second flip-flop having the same clock CLK_Das input data for the second flip-flop. Based on the output of the first flip-flop (e.g., output S) and of the second flip-flop (e.g., output S), the embodiments determine whether the rising and or falling edge of clock CLK_Dshould be used for triggering in a transmitting and receiving application. The embodiments are applicable in both situations where the rising edge or falling edge of clock CLK_Dis used as a triggering edge. Other embodiments are also disclosed.

Growing community of inventors

Chubei, Taiwan

Jinn-Yeh Chien