Industrial Technology Research Institute

Faraday Technology Corporation

Jinn-Shyan Wang

Yung-Jung Jan

Pei-Yuan Chou

Yeong-Jar Chang

Jinn-Nan Kao

Chuen-Shiu Chen

Hung-Yu Li

A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.

Time detection circuit and time detection method

An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.

On-chip apparatus and method for jitter measurement

A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

Leakage current control circuit with a single low voltage power supply and method thereof

An HDTV decoder comprises a variable length decoder for decoding variable length code words in parallel to generate fixed length code words. A buffer for buffering the fixed length code words is connected to an output of the variable length decoder. A run length decoder is connected to an output of the buffer for run length decoding the fixed length code words. The variable length decoder has the same input and output running speed, which running speed is larger than an average speed and smaller than a burst speed at which said parallel variable length decoder would have to operate in the absence of said buffer. When the variable length decoder is capable of decoding more than one variable length code word in a cycle, the required buffer is quite small. It may be less than 1 k byte and may be on the order of 100 bytes. In this case, the variable length decoder and buffer may be incorporated in a single integrated circuit.

HDTV decoder

A high speed variable length decoder can decode more than one code word in one cycle. A PLA used in the decoder includes extra product lines and extra output lines in order to detect and decode two successive short length code words in one cycle. When two short length code words are detected, a corresponding extra product line is activated and the two code words are decoded in the same cycle using an extra output line. For a digital video compression system, a significant speed-up in the variable length decoder can be achieved by the invention.

High speed variable length decoder

A circuit and algorithm for multiplying three matrices is disclosed having a first multiplication stage for multiplying a first matrix with a second matrix to produce an intermediate product matrix. Additionally, the circuit and algorithm have a second stage for multiplying a third matrix with the intermediate product matrix to compute the final product matrix. Each stage is provided with a plurality of bit processing element pipelines for generating the elements of the product matrix of that stage. In each stage, one pipeline is provided for generating each column of the product matrix and each pipeline within a stage operates in parallel with the other pipelines of that stage.

Growing community of inventors

Hsinchu, Taiwan

Jinn-Shyan Wang