Shenzhen China Star Optoelectronics Technology Co., Ltd.

Ledlucky Holdings Company Ltd.

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Jinming Li

Zheng Xiao

Peng Luo

Shaoqing Luo

A method for fabricating a display panel includes: forming a plurality of N-type doped amorphous silicon structures on a substrate; forming an amorphous silicon layer covering the N-type doped amorphous silicon structures and the substrate; blue laser annealing the amorphous silicon layer and the N-type doped amorphous silicon structures, so that the N-type doped amorphous silicon structures are converted into N-type heavily doped polysilicon structures, a part of the amorphous silicon layer in contact with one of the N-type doped amorphous silicon structures and located between two adjacent N-type doped amorphous silicon structures is converted into an N-type lightly doped polysilicon structure, and other parts of the amorphous silicon layer are converted into a polysilicon layer; and patterning the polysilicon layer to form a semiconductor layer.

Display panel and method for fabricating same

The present invention discloses a side-emitting LED panel lamp, where the side-emitting LED panel lamp includes a frame, a light-emitting element, a driving power supply, a backboard, a pressing bar, a light guide plate, and a diffusion plate; the light-emitting element, the driving power supply, and the backboard are disposed on a lower surface of the frame; the pressing bar is disposed around the backboard and covers the driving power supply; the driving power supply is electrically connected to the light-emitting element; the light guide plate is disposed on a lower surface of the backboard; the light guide plate is flush with the light-emitting element; and the diffusion plate is disposed on a lower surface of the light guide plate. In the present invention, all the components are integrally assembled. When used, the side-emitting LED panel lamp can be directly connected to a mains power supply, so as to avoid lamp damage caused because the light-emitting element does not match the driving power supply due to secondary adjustment, therefore facilitating a direct operation of a user.

LED side-luminescence panel lamp

The present invention discloses an intelligent induction miner's lamp. A heat dissipating portion in the miner's lamp includes a substrate, a reflector, and heat sinks; the substrate provided with a first through-hole in the center thereof is arranged on an inner wall of the reflector; an upper surface of the substrate is provided with a plurality of the heat sinks; the substrate, the reflector, and the heat sinks are integrated during casting; the power source cover is provided with a latching switch and is arranged on the reflector; the reflector is provided with a lens whose center is a recessed blind via; the lens is located on a side of a lower surface of the substrate, a ring protrusion is provided around the recessed blind via, and a sensor is arranged in the recessed blind via; the lens, the reflector, and the power source cover form a cavity; a driving power source fixed to the substrate is arranged in the cavity; and the lower surface of the substrate is provided with a light emitting element corresponding to the ring protrusion. In the present invention, the latching switch is arranged on the power source cover. Before the miner's lamp is mounted, whether the miner's lamp has a sensing function can be controlled by using the latching switch. In this way, use of other lamps of the same type is not affected, the costs are low, and mounting, cable layout, and subsequent maintenance are easy.

Intelligent induction miner's lamp

The present disclosure provides a method for manufacturing a thin film transistor comprising: forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed; forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions; etching the remaining aluminum layer after the annealing treatment; renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions, and oxidizing the conductor regions; stacking an insulating layer, and forming a source electrode and a drain electrode on the insulating layer.

Manufacturing method for thin film transistor and array substrate

The present disclosure proposes a TFT array substrate and a method of forming the same. The TFT array substrate includes a substrate, a semi-conductor layer, a pixel electrode on the substrate so to be on the same layer as the semi-conductor layer, a gate insulating layer, a gate electrode, an ILD layer on the substrate so to cover the gate insulating layer, gate electrode and pixel electrode, a source electrode on the ILD layer and connected to the semi-conductor layer, and a drain electrode on the ILD layer and connected to the semi-conductor layer and pixel electrode. The TFT array substrate can prevent etching of the metal oxide by an etching solution. The TFT array substrate having a top-gate structure, including with a traditional TFT with a top-gate structure, can skip the use of photomask at two occasions during the production process, thus lowers the production cost.

TFT array substrate and method of forming the same

The present disclosure relates to a low temperature poly-silicon thin film transistor and a method of preparing the same. The low temperature poly-silicon thin film transistor includes a substrate, a metal induction layer formed on the substrate, a barrier layer formed on the metal induction layer, and an amorphous silicon film layer formed on the barrier layer, the amorphous silicon film layer being converted into a poly-silicon film layer under the inducing effect of the metal induction layer, and the poly-silicon film layer being an active layer. In the present disclosure, although the active layer is obtained by using the metal induction method, the metal induction layer is provided below the amorphous silicon film layer, and a barrier layer is provided between the metal induction layer and the amorphous silicon film layer.

Low temperature poly-silicon thin film transistor and method of manufacturing the same

The present invention provides a low temperature poly-silicon thin-film transistor, as well as a manufacturing method thereof, which includes: a substrate (), a light shield layer () formed on the substrate (), a pad layer () formed on the light shield layer (), a dielectric layer () formed on the pad layer, an active layer () formed on the dielectric layer, a gate insulation layer () formed on the active layer (), and a gate layer () formed on the gate insulation layer (). The light shield layer () includes a planar section () formed on the substrate () and a raised section () formed on the planar section (). The active layer () has a projection that covers at least a partial area of an upper surface of the raised section () and one of sidewalls () of the raised section (). Without varying an aperture ratio of a display device, the channel width can be effectively increased and the width-to-length ratio can be increased so as to increase an open state current and enhance driving power of the LTPS TFT and device performance.

Low temperature poly-silicon thin-film transistor and manufacturing method thereof

A TFT includes a substrate, a gate, a gate insulating layer, a semiconductor oxide layer, a source/drain layer, a passivation layer, and a transparent conducting layer arranged from bottom to top. An etching block layer is formed after the source/drain layer arranged on the semiconductor oxide layer is etched. A method for forming for the TFT includes: depositing and photo-etching a gate on a substrate; depositing a gate insulating layer on the gate; depositing and photo-etching a semiconductor oxide layer on the gate insulating layer; depositing and photo-etching a source/drain layer on the semiconductor oxide layer; etching the source/drain layer on the semiconductor oxide layer for forming an etching block layer; depositing a passivation layer on the source/drain layer and the semiconductor oxide layer; depositing a transparent conducting layer on the passivation layer.

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Guangdong, China

Jinming Li