Silead Inc.

Jinling Zhou

Jun Yang

Hongzhen Chen

Wei Su

The present disclosure provides a method for controlling a fingerprint identification circuit. The method is used for detecting fingerprint recognition units arranged in an array. A fingerprint recognition unit is connected to a fingerprint recognition circuit. The fingerprint recognition circuit includes a loop selection unit and a signal processing unit. The method includes: resetting the fingerprint recognition circuit to enable the loop selection unit to load a first driving voltage to a sensing electrode; and, controlling a state of the loop selection unit through a sequence signal control to enable the fingerprint recognition units arranged in an array to be in different working states.

Fingerprint recognition circuit, method for controlling fingerprint recognition circuit, and chip

A touch detection circuit, a touch sensing chip and an electronic device are disclosed. The touch detection circuit includes charge/discharge circuits, which are configured to charge or discharge the sense channels during scanning periods to convert sense signals on the sense channels into sense voltages; a reference voltage generator circuit, which is coupled to the sense channels of the touch screen and is configured to produce a reference voltage related to the voltages on the sense channels; programmable gain amplifiers including first input terminals coupled to output terminals of the charge/discharge circuits and second input terminals coupled to an output terminal of the reference voltage generator circuit, the programmable gain amplifiers configured to amplify differences between the sense voltages and the reference voltage; analog-to-digital converters, which are coupled to the programmable gain amplifiers and are configured for quantization of the differences that have been amplified by the programmable gain amplifiers.

Touch detection circuit, touch sensing chip and electronic device

A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop; a second high-speed flip-flop; and a first logic gate, wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate. The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.

Data register unit, SAR ADC and electronic device

A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.

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Shanghai, China

Jinling Zhou