Skhynix Inc.

Jinliang Mao

Chee Hoe Chu

JongSu Lee

Embodiments of the present invention provide a PIPE5 to PIPE4 converter to provide compatibility between a PIPE5 controller and a PIPE4 test device. The converter includes a first interface coupled to the PIPE5 controller including MAC registers through a message bus interface, a second interface coupled to the PIPE4 device through a PCIe link and PHY registers. When a first message bus interface signal is received from the PIPE5 controller, the first interface finds a target PHY register based on the first message bus interface signal, and the second interface generates a first link interface signal associated with the target PHY register and outputs the first link interface signal to the PIPE4 device.

System including PIPE5 to PIPE4 converter and method thereof

Enabling an integrated circuit (IC) to accommodate a new peripheral component interconnect express (PCIe) capability of an updated PCIe specification. Firmware-programmable registers for the IC, spanning a target range of register and function numbers to accommodate the new capability, are created. A host issues configuration requests to the IC, which include a register and function number for the new capability. The IC returns a value of a target register when the register number and function number are in the target range. The host updates the value and triggers a firmware interrupt to add the new capability to a list of existing capabilities.

Configurable integrated circuit to support new capability

An apparatus includes a first address converter coupled to a first device and a second device and configured to convert a first n-bit address received from the first device into an m-bit upper address portion and an (n&#x2212;m)-bit lower address portion and forward the m-bit upper address through a side path and the (n&#x2212;m)-bit lower address portion through a main path to the second device, m and n are positive integers, and a second address converter configured to assemble the m-bit upper address portion and the (n&#x2212;m)-bit lower address portion to a second n-bit address that is a representation of the first n-bit address and provide the second n-bit address to a third device.

Addressing switch solution

An apparatus supporting a plurality of operational modes includes a physical interface having a plurality of lanes, an endpoint device having a plurality of interfaces, a plurality of multiplexers disposed between the physical interface and the endpoint device, and a controller configured to route a first portion of the lanes to a first portion of the interfaces through the multiplexers in response to a selected mode of the plurality of operational modes.

Configurable interface card

An apparatus for determining an eye mask of a device under test (DUT) which is configured to receive a data bit stream signal including a threshold level value and output a data bit stream output signal. The apparatus includes an input unit configured to receive the data bit stream output signal provided by the DUT, an evaluation unit configured to evaluate the received data bit output signal and provide an evaluation result, and a controller configured to change the threshold level value in response to the evaluation result. The apparatus is integrated into the DUT and can operates autonomously without multiple interactions with a tester.

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Milpitas, CA, United States of America

Jinliang Mao