Marvell International Limited

Marvellworld Trade Ltd.

Jinjin He

Fei Sun

Wei Xu

Tony Yoon

Bo Fu

Siu-Hung Frederick Au

Ka-Ming Keung

Hyunsuk Shin

Chi Kong Lee

ChengKuo Huang

Jungil Park

Young-Ta Wu

A method for storing data on a storage device includes receiving data to be stored and a logical address for storing the data. A physical address is determined and the data to be stored is stored at the determined physical address. A table that associates logical addresses with physical addresses is examined to determine a difference relationship between the determined physical address and a corresponding physical address for one of other logical addresses. Information representing the determined physical address is stored in the table, in association with the received logical address, as a function of the determined difference relationship. A data storage device includes controller circuitry and memory for storing a lookup table that associates logical addresses with physical addresses. The controller circuitry operates in accordance with the method.

Dynamic differential compression for storage device look-up table

Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.

Method and apparatus for compressing LUT

A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.

Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive

Systems and methods for managing storage device commands are provided. A first storage device command is received. A first priority associated with the first storage device command is identified. A plurality of storage device commands that was received before the first storage device command is identified. Each of the plurality of storage device commands is stored in a buffer and organized in a sequence. A determination is made as to whether the first priority associated with the first storage device command is greater than a second priority associated with a second storage device command of the plurality of storage device commands. The first storage device command is added to the buffer at a first position in the sequence that is earlier than a second position of the second storage device command in response to determining the first priority is greater than the second priority.

Methods and apparatus for managing storage device commands

The present disclosure includes systems and techniques relating to adjusting bit reliability information input for decoding data stored in a memory device. In some implementations, an apparatus, systems, or methods can include a memory controller that includes circuitry configured to receive data from a memory device, where the data includes at least first and second states; circuitry configured to compare a number of the first and second states of the received data; and circuitry configured to adjust a bit reliability information input to a decoder based, at least in part, on the comparison.

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San Jose, CA, United States of America

Jinjin He