Fujitsu Corporation

Nec Corporation

Jinichi Yoshizawa

Junichi Tamura

Hiroyuki Sato

Hiroichi Nara

Hiroomi Tateishi

Haruo Yamashita

Akihiro Yasuo

Takeshi Sasaki

Tatsuya Oku

Eiji Maeda

Hiroshi Okagawa

Tsuguo Okada

Shigeatsu Samukawa

Masao Hayashi

Masayoshi Sekido

Masao Maeda

Yoshinori Okuda

Akira Yamamori

The process of transferring a packet including a multicast packet can be performed at a high speed, and the output order between unicast and multicast can be guaranteed by a system including a unitfor determining an output port through which a packet input through an input port is to be output, and assigning output order identification information to the packet, a unitfor storing data of an input packet; and units,, . . . which correspond to each of a plurality of output ports, reading data of a packet determined by the unitto be output through a corresponding output port from the unitin the output order indicated by output order identification information, and outputs the read data through a corresponding output port.

Packet transfer path control apparatus and control program therefor

In multi-connections, a message writing apparatus is provided. This message writing apparatus () comprises a path recognizing section (), a received message assembling section (), a receive control section (), an arbitrating section () and an external memory control section (). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.

Message writing apparatus, message writing method, message readout apparatus, message readout method, memory address control circuit for writing of variable-length message and memory address control circuit for readout of variable-length message

A terminating apparatus for an ATM adaptation layer is made of hardware logic circuits to terminate received cells connection by connection and assemble an ATM adaptation layer message for each connection from data contained in the received cells. The apparatus is compact and operates at high speed. The structure of the apparatus is independent of the number of connections to terminate. The apparatus has a-header extractor ( - ) for extracting a virtual path indication/virtual channel indication (VPI/VCI) from a received cell, a CRC unit ( - ) shared by cells of different connections, a reception processor ( - ) for determining whether or not the received cell is the last cell of an ATM adaptation layer message according to a payload type indication (PTI) contained in a header of the received cell and processing the received cell, a work memory ( - ) for storing, for each connection, a CRC result and the number of received cells, and a reception buffer ( - ) for sequentially storing, for each connection, data contained in cells received for the connection.

Terminating apparatus for ATM adaptation layer

A data transfer system includes a plurality of functional blocks each provided with a function module for controlling data transfer between memories of the plurality of functional blocks, by being connected to a function module of other functional blocks via n sets of data signal lines and clock signal lines so that the data transfer proceeds in a synchronized manner. Each of the n sets of data signal lines and clock signal lines is appropriately combined with one another depending on a required condition for communicating with destination functional blocks, such that a plurality of sets of data signal lines and clock signal lines are used for parallel transfer and a single set of a data signal line and a clock signal line is used for serial transfer.

Combining plural data lines and clock lines into set of parallel lines

Disclosed is a method of sending and receiving setting information and monitoring information between a monitoring controller and units which construct the multiplexing section of a communication apparatus. In a case where setting information is transferred from the monitoring controller to a prescribed unit, the monitoring controller time-division multiplexes the setting information for the unit and enters the information into a time switch via an incoming line. The time switch switches the time slot position of the setting information and sends the setting information to an outgoing line corresponding to the unit. The unit drops the setting information from the time slot. Further, in a case where monitoring information is transferred from a unit to the monitoring controller, the unit time-division multiplexes the monitoring information to a predetermined time slot and enters the monitoring information into the time switch from a prescribed line. The time switch switches the time slot position of the monitoring information and sends the monitoring information to the monitoring controller via an outgoing line. The monitoring controller accepts the monitoring information from the unit, with the information coming from the above-mentioned time slot.

Method of sending and receiving setting information and monitoring

Disclosed is a clock distributing apparatus for distributing clock signals with a desired phase to each of devices provided between a clock generating section (10) for generating clock signals and a plurality of devices (30) for receiving the clock signals. A delay generating section (21) generates a plurality of delay clock signals by imparting a plurality of delay quantities to the clock signals from the clock generating section. A clock distributing section (22) has a plurality of input terminals corresponding to the plurality of delay clock signals and a plurality of output terminals corresponding to the respective devices. The clock distributing section (22) distributes desired delay clock signals to one or more output terminals by selecting the input terminals corresponding to the desired delay clock signals.

Clock distributing method and apparatus

A write address counter for designating a write address of a memory counts up a control counter with an address change. A read address counter for designating a read address of the memory counts down the control counter with the address change. Inputted to an error detecting circuit are a write address counter value, a read address counter value and a control count value. There is detected whether a relationship such as Write Address Count Value-Read Address Count Value=Control Count Value is established or not. If not established, this implies an error, and a reset circuit resets each counter.

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Kawasaki, Japan

Jinichi Yoshizawa