Samsung Electronics Co., Ltd.

Seoul National University

Jinhyuk Kim

Jung-Hwan Kim

Seungmin Song

Joongshik Shin

Sunggil Kim

Yongjin Kwon

Donggi Lee

Taesung Jung

Dae-Kyu Park

Chaesuk Lim

Duckhyun Chang

Beyounghyun Koh

Mi Kyoung Jang

Wonchuri Zoo

Byungse So

Bryan Suk Joon Kim

Hongik Son

Taekkyun Lee

Han-Chan Jo

SangLyul Min

A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

Semiconductor device having a stack including electrodes vertically stacked on a substrate and electronic system including the same

A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

Semiconductor device and electronic system including the same

A management method for a memory system executes a first memory system management sequence upon determining that the memory system was normally powered off, and a second sequence upon determining that the memory system was abnormally powered off. The first sequence allows immediate execution of a program operation at a valid data page location extracted from stored metadata, while the second sequence allows execution of a program operation only after programming dummy data to at least one erroneous page.

Management method for nonvolatile memory system following power-off

A method is provided for writing data in a storage device, including a nonvolatile memory. The method includes receiving a pre-write command including a logical address and size information of write data, performing a pre-operation for optimization of a write operation based on the pre-write command, and writing the write data in the nonvolatile memory after the pre-operation is completed.

Data storage device and method of writing data in the same

Provided are a flash memory system and a driving method thereof. A flash memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, and a control logic. The control logic performs control for one-bit information to be stored in the plurality of memory cells. The control logic controls storing data in the plurality of memory cells multiple times without an erasion operation. Accordingly, the flash memory device does not execute an erasion operation, increasing an operation speed.

Memory device and program method thereof

Growing community of inventors

Hwaseong-si, South Korea

Jinhyuk Kim