Samsung Electronics Co., Ltd.

JinHyeok Choi

Hwaseok Oh

Youngmin Lee

Sungho Seo

Hyuntae Park

Youngjin Cho

Sun-Young Lim

Chankyung Kim

Uksong Kang

Sungyong Seo

Duckhyun Chang

Yongwoo Jeong

Ji-Seung Youn

Han-Ju Lee

Kwanwoo Noh

Youngkwang Yoo

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

Nonvolatile memory device and operation method thereof

Disclosed is a storage device which includes a nonvolatile memory device and a controller. The controller communicates with a host through a first port, communicates with an external storage device through a second port, and controls the nonvolatile memory device based on first mapping information. The controller is configured to receive second mapping information from the external storage device, receive first write data from the host and to selectively transmit first write data to the external storage device based on the second mapping information.

Storage device, user device including storage device, and operation method of user device

Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.

Electronic device comprising storage devices transmitting reference clock via cascade coupling structure

According to at least some example embodiments of the inventive concepts, an electronic device includes an embedded storage device that is, configured to connect to a removable storage device, and configured to directly communicate with the removable storage device, when connected to the removable storage device; and an application processor connected to directly communicate with the embedded storage device and not directly connected with the removable storage device, wherein, the embedded storage device is configured to, in response to a disable command received from the application processor, decrease an amount of power supplied to all or some of circuits included in the embedded storage device, and provide a bypass path that is configured to transfer a normal command and data from the application processor to the removable storage device, when the removable storage device is connected to the bypass path.

Electronic device providing bypass path to indirectly connected storage device among serially connected storage devices, storage device included therein, computing system including the same, and method of communicating therewith

An electronic device includes an application processor; and a first storage device that is, connected to the application processor and directly communicates with the application processor, and connected to a second storage device such that the second storage device communicates with the application processor through the first storage device, wherein the first storage device includes a reset converter configured to generate a software reset signal in response to a hardware reset signal received from the application processor, and wherein the software reset signal resets the second storage device.

Electronic device configured to reset storage device non-directly connected to application processor among storage devices serially connected to one another and method of operating the same

An electronic device may include an embedded storage device connected to directly communicate with an extended storage device, and an application processor connected to directly communicate with the embedded storage device and connected to the extended storage device through the embedded storage device. The embedded storage device includes a monitoring device that monitors commands received from the application processor. The monitoring device generates a command state signal representing a state of the embedded storage device and the extended storage device based on a result of monitoring the commands. The embedded storage device operates so that a power supply is controlled in a part or all of the embedded storage device according to the command state signal.

Electronic device including monitoring circuit and storage device included therein

An electronic device includes an embedded storage device and an application processor. The embedded storage device is connected to directly communicate with a removable storage device which processes a packet having a first characteristic. The embedded storage device processes a packet having a second characteristic. The application processor is connected to directly communicate with the embedded storage device, but not directly connected to the removable storage device. The application processor processes a packet having a third characteristic. The embedded storage device compensates at least one of the first characteristic or the second characteristic, such that at least one of a first packet of the first characteristic received from the removable storage device or a second packet of the second characteristic in the embedded storage device is provided to the application processor according to the third characteristic.

Electronic device compensating different characteristics of serially connected storage devices and storage device included therein

A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

Nonvolatile memory modules comprising volatile memory devices and nonvolatile memory devices

Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ECC) when the error of the data read according to the first read condition is correctable.

Nonvolatile memory devices with age-based variability of read operations and methods of operating same

Integrated circuit memory systems include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells. This modification occurs in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle.

A method for correcting read data error of a nonvolatile memory device, the error correction method including performing a first read operation of applying a first non-selection read voltage to a plurality of unselected memory cells to read a plurality of selected memory cells, performing a second read operation of applying a second non-selection read voltage less than the first non-selection read voltage to the unselected memory cells to read the selected memory cells, and comparing data sensed in the first and second read operations to detect error locations of read data.

Growing community of inventors

Yongin-si, South Korea

JinHyeok Choi