Samsung Electronics Co., Ltd.

Jinhyeok Baek

Jeongdon Ihm

Hun-Dae Choi

Changsik Yoo

Hangi Jung

Yonghun Kim

Jaemin Choi

Yoochang Sung

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

Interface circuit and operating method thereof to compensate for supply voltage variations

A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.

Semiconductor memory device for calibrating a termination resistance and a method of calibrating the termination resistance thereof

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Busan, South Korea

Jinhyeok Baek